Commit e3bb599d authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree 



Convert the VRINTA/VRINTN/VRINTP/VRINTM instructions to decodetree.
Again, trans_VRINT() is temporarily left in translate.c.

Signed-off-by: default avatarPeter Maydell &lt;peter.maydell@linaro.org&gt;Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
parent f65988a1

target/arm/translate.c

+38 −22
Original line number Diff line number Diff line
@@ -3270,11 +3270,43 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a) 
    return true;

}



static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,

                        int rounding)

/*

 * Table for converting the most common AArch32 encoding of

 * rounding mode to arm_fprounding order (which matches the

 * common AArch64 order); see ARM ARM pseudocode FPDecodeRM().

 */

static const uint8_t fp_decode_rm[] = {

    FPROUNDING_TIEAWAY,

    FPROUNDING_TIEEVEN,

    FPROUNDING_POSINF,

    FPROUNDING_NEGINF,

};



static bool trans_VRINT(DisasContext *s, arg_VRINT *a)

{

    TCGv_ptr fpst = get_fpstatus_ptr(0);

    uint32_t rd, rm;

    bool dp = a->dp;

    TCGv_ptr fpst;

    TCGv_i32 tcg_rmode;

    int rounding = fp_decode_rm[a->rm];



    if (!dc_isar_feature(aa32_vrint, s)) {

        return false;

    }



    /* UNDEF accesses to D16-D31 if they don't exist */

    if (dp && !dc_isar_feature(aa32_fp_d32, s) &&

        ((a->vm | a->vd) & 0x10)) {

        return false;

    }

    rd = a->vd;

    rm = a->vm;



    if (!vfp_access_check(s)) {

        return true;

    }



    fpst = get_fpstatus_ptr(0);



    tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));

    gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
@@ -3305,7 +3337,7 @@ static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp, 
    tcg_temp_free_i32(tcg_rmode);



    tcg_temp_free_ptr(fpst);

    return 0;

    return true;

}



static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
@@ -3366,17 +3398,6 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp, 
    return 0;

}



/* Table for converting the most common AArch32 encoding of

 * rounding mode to arm_fprounding order (which matches the

 * common AArch64 order); see ARM ARM pseudocode FPDecodeRM().

 */

static const uint8_t fp_decode_rm[] = {

    FPROUNDING_TIEAWAY,

    FPROUNDING_TIEEVEN,

    FPROUNDING_POSINF,

    FPROUNDING_NEGINF,

};



static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn)

{

    uint32_t rd, rm, dp = extract32(insn, 8, 1);
@@ -3389,12 +3410,7 @@ static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn) 
        rm = VFP_SREG_M(insn);

    }



    if ((insn & 0x0fbc0ed0) == 0x0eb80a40 &&

        dc_isar_feature(aa32_vrint, s)) {

        /* VRINTA, VRINTN, VRINTP, VRINTM */

        int rounding = fp_decode_rm[extract32(insn, 16, 2)];

        return handle_vrint(insn, rd, rm, dp, rounding);

    } else if ((insn & 0x0fbc0e50) == 0x0ebc0a40 &&

    if ((insn & 0x0fbc0e50) == 0x0ebc0a40 &&

        dc_isar_feature(aa32_vcvt_dr, s)) {

        /* VCVTA, VCVTN, VCVTP, VCVTM */

        int rounding = fp_decode_rm[extract32(insn, 16, 2)];

target/arm/vfp-uncond.decode

+5 −0
Original line number Diff line number Diff line
@@ -50,3 +50,8 @@ VMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \ 
            vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0

VMINMAXNM   1111 1110 1.00 .... .... 1011 . op:1 .0 .... \

            vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1



VRINT       1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \

            vm=%vm_sp vd=%vd_sp dp=0

VRINT       1111 1110 1.11 10 rm:2 .... 1011 01.0 .... \

            vm=%vm_dp vd=%vd_dp dp=1