Commit e32c41e4 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into staging 



target/xtensa updates:

- refactor CCOUNT/CCOMPARE (use QEMU timers instead of instruction counting);
- support icount; run target/xtensa TCG tests with icount;
- implement SMP prerequisites: static vector selection, RUNSTALL and RER/WER.

# gpg: Signature made Wed 25 Jan 2017 00:27:51 GMT
# gpg:                using RSA key 0x51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>"
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20170124-xtensa:
  target-xtensa: implement RER/WER instructions
  target/xtensa: tests: clean up interrupt tests
  target/xtensa: tests: add memctl test
  target/xtensa: implement MEMCTL SR
  target/xtensa: fix ICACHE/DCACHE options detection
  target/xtensa: tests: add ccount write tests
  target/xtensa: tests: replace hardcoded interrupt masks
  target/xtensa: tests: fix timer tests
  target/xtensa: tests: run tests with icount
  target/xtensa: don't continue translation after exception
  target/xtensa: support icount
  target/xtensa: refactor CCOUNT/CCOMPARE
  target/xtensa: implement RUNSTALL
  target/xtensa: add static vectors selection

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents ae5045ae 3a3c9dc4

hw/xtensa/pic_cpu.c

+14 −61
Original line number Diff line number Diff line
@@ -31,22 +31,6 @@ 
#include "qemu/log.h"

#include "qemu/timer.h"



void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d)

{

    uint32_t old_ccount = env->sregs[CCOUNT] + 1;



    env->sregs[CCOUNT] += d;



    if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {

        int i;

        for (i = 0; i < env->config->nccompare; ++i) {

            if (env->sregs[CCOMPARE + i] - old_ccount < d) {

                xtensa_timer_irq(env, i, 1);

            }

        }

    }

}



void check_interrupts(CPUXtensaState *env)

{

    CPUState *cs = CPU(xtensa_env_get_cpu(env));
@@ -54,17 +38,6 @@ void check_interrupts(CPUXtensaState *env) 
    uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];

    int level;



    /* If the CPU is halted advance CCOUNT according to the QEMU_CLOCK_VIRTUAL time

     * elapsed since the moment when it was advanced last time.

     */

    if (cs->halted) {

        int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);



        xtensa_advance_ccount(env,

                muldiv64(now - env->halt_clock,

                    env->config->clock_freq_khz, 1000000));

        env->halt_clock = now;

    }

    for (level = env->config->nlevel; level > minlevel; --level) {

        if (env->config->level_mask[level] & int_set_enabled) {

            env->pending_irq_level = level;
@@ -109,49 +82,29 @@ void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active) 
    qemu_set_irq(env->irq_inputs[env->config->timerint[id]], active);

}



void xtensa_rearm_ccompare_timer(CPUXtensaState *env)

{

    int i;

    uint32_t wake_ccount = env->sregs[CCOUNT] - 1;



    for (i = 0; i < env->config->nccompare; ++i) {

        if (env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] <

                wake_ccount - env->sregs[CCOUNT]) {

            wake_ccount = env->sregs[CCOMPARE + i];

        }

    }

    env->wake_ccount = wake_ccount;

    timer_mod(env->ccompare_timer, env->halt_clock +

            (uint64_t)(wake_ccount - env->sregs[CCOUNT]) *

            1000000 / env->config->clock_freq_khz);

}



static void xtensa_ccompare_cb(void *opaque)

{

    XtensaCPU *cpu = opaque;

    CPUXtensaState *env = &cpu->env;

    CPUState *cs = CPU(cpu);

    XtensaCcompareTimer *ccompare = opaque;

    CPUXtensaState *env = ccompare->env;

    unsigned i = ccompare - env->ccompare;



    if (cs->halted) {

        env->halt_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);

        xtensa_advance_ccount(env, env->wake_ccount - env->sregs[CCOUNT]);

        if (!cpu_has_work(cs)) {

            env->sregs[CCOUNT] = env->wake_ccount + 1;

            xtensa_rearm_ccompare_timer(env);

        }

    }

    xtensa_timer_irq(env, i, 1);

}



void xtensa_irq_init(CPUXtensaState *env)

{

    XtensaCPU *cpu = xtensa_env_get_cpu(env);



    env->irq_inputs = (void **)qemu_allocate_irqs(

            xtensa_set_irq, env, env->config->ninterrupt);

    if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT) &&

            env->config->nccompare > 0) {

        env->ccompare_timer =

            timer_new_ns(QEMU_CLOCK_VIRTUAL, &xtensa_ccompare_cb, cpu);

    if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {

        unsigned i;



        env->time_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);

        env->ccount_base = env->sregs[CCOUNT];

        for (i = 0; i < env->config->nccompare; ++i) {

            env->ccompare[i].env = env;

            env->ccompare[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,

                    xtensa_ccompare_cb, env->ccompare + i);

        }

    }

}

target/xtensa/cpu.c

+10 −2
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ static bool xtensa_cpu_has_work(CPUState *cs) 
{

    XtensaCPU *cpu = XTENSA_CPU(cs);



    return cpu->env.pending_irq_level;

    return !cpu->env.runstall && cpu->env.pending_irq_level;

}



/* CPUClass::reset() */
@@ -60,12 +60,13 @@ static void xtensa_cpu_reset(CPUState *s) 
    xcc->parent_reset(s);



    env->exception_taken = 0;

    env->pc = env->config->exception_vector[EXC_RESET];

    env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];

    env->sregs[LITBASE] &= ~1;

    env->sregs[PS] = xtensa_option_enabled(env->config,

            XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;

    env->sregs[VECBASE] = env->config->vecbase;

    env->sregs[IBREAKENABLE] = 0;

    env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;

    env->sregs[CACHEATTR] = 0x22222222;

    env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,

            XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
@@ -74,6 +75,7 @@ static void xtensa_cpu_reset(CPUState *s) 


    env->pending_irq_level = 0;

    reset_mmu(env);

    s->halted = env->runstall;

}



static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
@@ -125,6 +127,12 @@ static void xtensa_cpu_initfn(Object *obj) 
    cs->env_ptr = env;

    env->config = xcc->config;



    env->address_space_er = g_malloc(sizeof(*env->address_space_er));

    env->system_er = g_malloc(sizeof(*env->system_er));

    memory_region_init_io(env->system_er, NULL, NULL, env, "er",

                          UINT64_C(0x100000000));

    address_space_init(env->address_space_er, env->system_er, "ER");



    if (tcg_enabled() && !tcg_inited) {

        tcg_inited = true;

        xtensa_translate_init();

target/xtensa/cpu.h

+53 −7
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ enum { 
    XTENSA_OPTION_PROCESSOR_ID,

    XTENSA_OPTION_DEBUG,

    XTENSA_OPTION_TRACE_PORT,

    XTENSA_OPTION_EXTERN_REGS,

};



enum {
@@ -129,6 +130,7 @@ enum { 
    ITLBCFG = 91,

    DTLBCFG = 92,

    IBREAKENABLE = 96,

    MEMCTL = 97,

    CACHEATTR = 98,

    ATOMCTL = 99,

    IBREAKA = 128,
@@ -189,6 +191,20 @@ enum { 
#define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)

#define DBREAKC_MASK 0x3f



#define MEMCTL_INIT 0x00800000

#define MEMCTL_IUSEWAYS_SHIFT 18

#define MEMCTL_IUSEWAYS_LEN 5

#define MEMCTL_IUSEWAYS_MASK 0x007c0000

#define MEMCTL_DALLOCWAYS_SHIFT 13

#define MEMCTL_DALLOCWAYS_LEN 5

#define MEMCTL_DALLOCWAYS_MASK 0x0003e000

#define MEMCTL_DUSEWAYS_SHIFT 8

#define MEMCTL_DUSEWAYS_LEN 5

#define MEMCTL_DUSEWAYS_MASK 0x00001f00

#define MEMCTL_ISNP 0x4

#define MEMCTL_DSNP 0x2

#define MEMCTL_IL0EN 0x1



#define MAX_NAREG 64

#define MAX_NINTERRUPT 32

#define MAX_NLEVEL 6
@@ -209,7 +225,8 @@ enum { 


enum {

    /* Static vectors */

    EXC_RESET,

    EXC_RESET0,

    EXC_RESET1,

    EXC_MEMORY_ERROR,



    /* Dynamic vectors */
@@ -268,6 +285,8 @@ typedef enum { 
    INTTYPE_MAX

} interrupt_type;



struct CPUXtensaState;



typedef struct xtensa_tlb_entry {

    uint32_t vaddr;

    uint32_t paddr;
@@ -297,6 +316,11 @@ typedef struct XtensaGdbRegmap { 
    XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];

} XtensaGdbRegmap;



typedef struct XtensaCcompareTimer {

    struct CPUXtensaState *env;

    QEMUTimer *timer;

} XtensaCcompareTimer;



struct XtensaConfig {

    const char *name;

    uint64_t options;
@@ -324,6 +348,10 @@ struct XtensaConfig { 
    unsigned nibreak;

    unsigned ndbreak;



    unsigned icache_ways;

    unsigned dcache_ways;

    uint32_t memctl_mask;



    uint32_t configid[2];



    uint32_t clock_freq_khz;
@@ -365,14 +393,19 @@ typedef struct CPUXtensaState { 
    xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];

    xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];

    unsigned autorefill_idx;



    bool runstall;

    AddressSpace *address_space_er;

    MemoryRegion *system_er;

    int pending_irq_level; /* level of last raised IRQ */

    void **irq_inputs;

    QEMUTimer *ccompare_timer;

    uint32_t wake_ccount;

    int64_t halt_clock;

    XtensaCcompareTimer ccompare[MAX_NCCOMPARE];

    uint64_t time_base;

    uint64_t ccount_time;

    uint32_t ccount_base;



    int exception_taken;

    int yield_needed;

    unsigned static_vectors;



    /* Watchpoints for DBREAK registers */

    struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
@@ -437,9 +470,7 @@ void xtensa_register_core(XtensaConfigList *node); 
void check_interrupts(CPUXtensaState *s);

void xtensa_irq_init(CPUXtensaState *env);

void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);

void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);

void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);

void xtensa_rearm_ccompare_timer(CPUXtensaState *env);

int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);

void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);

void xtensa_sync_window_from_phys(CPUXtensaState *env);
@@ -460,7 +491,18 @@ int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, 
void reset_mmu(CPUXtensaState *env);

void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);

void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);

static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)

{

    return env->system_er;

}



static inline void xtensa_select_static_vectors(CPUXtensaState *env,

                                                unsigned n)

{

    assert(n < 2);

    env->static_vectors = n;

}

void xtensa_runstall(CPUXtensaState *env, bool runstall);



#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))

#define XTENSA_OPTION_ALL (~(uint64_t)0)
@@ -539,6 +581,7 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) 
#define XTENSA_TBFLAG_EXCEPTION 0x4000

#define XTENSA_TBFLAG_WINDOW_MASK 0x18000

#define XTENSA_TBFLAG_WINDOW_SHIFT 15

#define XTENSA_TBFLAG_YIELD 0x20000



static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,

        target_ulong *cs_base, uint32_t *flags)
@@ -580,6 +623,9 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, 
    } else {

        *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;

    }

    if (env->yield_needed) {

        *flags |= XTENSA_TBFLAG_YIELD;

    }

}



#include "exec/cpu-all.h"

target/xtensa/helper.c

+13 −0
Original line number Diff line number Diff line
@@ -728,3 +728,16 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env) 
        cpu_fprintf(f, "No TLB for this CPU core\n");

    }

}



void xtensa_runstall(CPUXtensaState *env, bool runstall)

{

    CPUState *cpu = CPU(xtensa_env_get_cpu(env));



    env->runstall = runstall;

    cpu->halted = runstall;

    if (runstall) {

        cpu_interrupt(cpu, CPU_INTERRUPT_HALT);

    } else {

        cpu_reset_interrupt(cpu, CPU_INTERRUPT_HALT);

    }

}

target/xtensa/helper.h

+7 −2
Original line number Diff line number Diff line
@@ -16,10 +16,12 @@ DEF_HELPER_1(simcall, void, env) 
DEF_HELPER_1(dump_state, void, env)



DEF_HELPER_3(waiti, void, env, i32, i32)

DEF_HELPER_3(timer_irq, void, env, i32, i32)

DEF_HELPER_2(advance_ccount, void, env, i32)

DEF_HELPER_1(update_ccount, void, env)

DEF_HELPER_2(wsr_ccount, void, env, i32)

DEF_HELPER_2(update_ccompare, void, env, i32)

DEF_HELPER_1(check_interrupts, void, env)

DEF_HELPER_3(check_atomctl, void, env, i32, i32)

DEF_HELPER_2(wsr_memctl, void, env, i32)



DEF_HELPER_2(itlb_hit_test, void, env, i32)

DEF_HELPER_2(wsr_rasid, void, env, i32)
@@ -54,3 +56,6 @@ DEF_HELPER_4(olt_s, void, env, i32, f32, f32) 
DEF_HELPER_4(ult_s, void, env, i32, f32, f32)

DEF_HELPER_4(ole_s, void, env, i32, f32, f32)

DEF_HELPER_4(ule_s, void, env, i32, f32, f32)



DEF_HELPER_2(rer, i32, env, i32)

DEF_HELPER_3(wer, void, env, i32, i32)