Loading target-i386/kvm.c +6 −21 Original line number Diff line number Diff line Loading @@ -1487,24 +1487,16 @@ static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value) static int kvm_put_tscdeadline_msr(X86CPU *cpu) { CPUX86State *env = &cpu->env; struct { struct kvm_msrs info; struct kvm_msr_entry entries[1]; } msr_data; struct kvm_msr_entry *msrs = msr_data.entries; int ret; if (!has_msr_tsc_deadline) { return 0; } kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline); msr_data.info = (struct kvm_msrs) { .nmsrs = 1, }; kvm_msr_buf_reset(cpu); kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline); ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { return ret; } Loading @@ -1521,24 +1513,17 @@ static int kvm_put_tscdeadline_msr(X86CPU *cpu) */ static int kvm_put_msr_feature_control(X86CPU *cpu) { struct { struct kvm_msrs info; struct kvm_msr_entry entry; } msr_data; int ret; if (!has_msr_feature_control) { return 0; } kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL, kvm_msr_buf_reset(cpu); kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, cpu->env.msr_ia32_feature_control); msr_data.info = (struct kvm_msrs) { .nmsrs = 1, }; ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { return ret; } Loading Loading
target-i386/kvm.c +6 −21 Original line number Diff line number Diff line Loading @@ -1487,24 +1487,16 @@ static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value) static int kvm_put_tscdeadline_msr(X86CPU *cpu) { CPUX86State *env = &cpu->env; struct { struct kvm_msrs info; struct kvm_msr_entry entries[1]; } msr_data; struct kvm_msr_entry *msrs = msr_data.entries; int ret; if (!has_msr_tsc_deadline) { return 0; } kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline); msr_data.info = (struct kvm_msrs) { .nmsrs = 1, }; kvm_msr_buf_reset(cpu); kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline); ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { return ret; } Loading @@ -1521,24 +1513,17 @@ static int kvm_put_tscdeadline_msr(X86CPU *cpu) */ static int kvm_put_msr_feature_control(X86CPU *cpu) { struct { struct kvm_msrs info; struct kvm_msr_entry entry; } msr_data; int ret; if (!has_msr_feature_control) { return 0; } kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL, kvm_msr_buf_reset(cpu); kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, cpu->env.msr_ia32_feature_control); msr_data.info = (struct kvm_msrs) { .nmsrs = 1, }; ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { return ret; } Loading