Commit e2382972 authored by Richard Henderson's avatar Richard Henderson
Browse files

tcg/ppc: Add support for vector maximum/minimum 



Add support for vector maximum/minimum using Altivec instructions
VMAXSB, VMAXSH, VMAXSW, VMAXUB, VMAXUH, VMAXUW, and
VMINSB, VMINSH, VMINSW, VMINUB, VMINUH, VMINUW.

Tested-by: default avatarMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
parent 6ef14d7e

tcg/ppc/tcg-target.h

+1 −1
Original line number Diff line number Diff line
@@ -164,7 +164,7 @@ extern bool have_altivec; 
#define TCG_TARGET_HAS_cmp_vec          1

#define TCG_TARGET_HAS_mul_vec          0

#define TCG_TARGET_HAS_sat_vec          0

#define TCG_TARGET_HAS_minmax_vec       0

#define TCG_TARGET_HAS_minmax_vec       1

#define TCG_TARGET_HAS_bitsel_vec       0

#define TCG_TARGET_HAS_cmpsel_vec       0

tcg/ppc/tcg-target.inc.c

+39 −1
Original line number Diff line number Diff line
@@ -471,6 +471,19 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, 
#define STVX       XO31(231)

#define STVEWX     XO31(199)



#define VMAXSB     VX4(258)

#define VMAXSH     VX4(322)

#define VMAXSW     VX4(386)

#define VMAXUB     VX4(2)

#define VMAXUH     VX4(66)

#define VMAXUW     VX4(130)

#define VMINSB     VX4(770)

#define VMINSH     VX4(834)

#define VMINSW     VX4(898)

#define VMINUB     VX4(514)

#define VMINUH     VX4(578)

#define VMINUW     VX4(642)



#define VCMPEQUB   VX4(6)

#define VCMPEQUH   VX4(70)

#define VCMPEQUW   VX4(134)
@@ -2817,6 +2830,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 
    case INDEX_op_andc_vec:

    case INDEX_op_not_vec:

        return 1;

    case INDEX_op_smax_vec:

    case INDEX_op_smin_vec:

    case INDEX_op_umax_vec:

    case INDEX_op_umin_vec:

        return vece <= MO_32;

    case INDEX_op_cmp_vec:

        return vece <= MO_32 ? -1 : 0;

    default:
@@ -2914,7 +2932,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 
    static const uint32_t

        eq_op[4]  = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },

        gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },

        gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 };

        gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },

        umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 },

        smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 },

        umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 },

        smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 };



    TCGType type = vecl + TCG_TYPE_V64;

    TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
@@ -2931,6 +2953,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 
        tcg_out_dupm_vec(s, type, vece, a0, a1, a2);

        return;



    case INDEX_op_smin_vec:

        insn = smin_op[vece];

        break;

    case INDEX_op_umin_vec:

        insn = umin_op[vece];

        break;

    case INDEX_op_smax_vec:

        insn = smax_op[vece];

        break;

    case INDEX_op_umax_vec:

        insn = umax_op[vece];

        break;

    case INDEX_op_and_vec:

        insn = VAND;

        break;
@@ -3223,6 +3257,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) 
    case INDEX_op_andc_vec:

    case INDEX_op_orc_vec:

    case INDEX_op_cmp_vec:

    case INDEX_op_smax_vec:

    case INDEX_op_smin_vec:

    case INDEX_op_umax_vec:

    case INDEX_op_umin_vec:

        return &v_v_v;

    case INDEX_op_not_vec:

    case INDEX_op_dup_vec: