Commit e1fa1164 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement SVE Bitwise Immediate Group 



Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-24-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 24e82e68

target/arm/sve.decode

+17 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ 


&rr_esz         rd rn esz

&rri            rd rn imm

&rr_dbm         rd rn dbm

&rrri           rd rn rm imm

&rri_esz        rd rn imm esz

&rrr_esz        rd rn rm esz
@@ -111,6 +112,10 @@ 
@rd_rn_tszimm   ........ .. ... ... ...... rn:5 rd:5 \

                &rri_esz esz=%tszimm16_esz



# Two register operand, one encoded bitmask.

@rdn_dbm        ........ .. .... dbm:13 rd:5 \

                &rr_dbm rn=%reg_movprfx



# Basic Load/Store with 9-bit immediate offset

@pd_rn_i9       ........ ........ ...... rn:5 . rd:4    \

                &rri imm=%imm9_16_10
@@ -330,6 +335,18 @@ INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1 
# Note these require esz != 0.

SINCDEC_v       00000100 .. 1 0 .... 1100 d:1 u:1 ..... .....   @incdec2_cnt



### SVE Bitwise Immediate Group



# SVE bitwise logical with immediate (unpredicated)

ORR_zzi         00000101 00 0000 ............. .....            @rdn_dbm

EOR_zzi         00000101 01 0000 ............. .....            @rdn_dbm

AND_zzi         00000101 10 0000 ............. .....            @rdn_dbm



# SVE broadcast bitmask immediate

DUPM            00000101 11 0000 dbm:13 rd:5



### SVE Predicate Logical Operations Group



# SVE predicate logical operations

AND_pppp        00100101 0. 00 .... 01 .... 0 .... 0 ....       @pd_pg_pn_pm_s

BIC_pppp        00100101 0. 00 .... 01 .... 0 .... 1 ....       @pd_pg_pn_pm_s

target/arm/translate-sve.c

+49 −0
Original line number Diff line number Diff line
@@ -1785,6 +1785,55 @@ static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a, 
    return true;

}



/*

 *** SVE Bitwise Immediate Group

 */



static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn)

{

    uint64_t imm;

    if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1),

                                extract32(a->dbm, 0, 6),

                                extract32(a->dbm, 6, 6))) {

        return false;

    }

    if (sve_access_check(s)) {

        unsigned vsz = vec_full_reg_size(s);

        gvec_fn(MO_64, vec_full_reg_offset(s, a->rd),

                vec_full_reg_offset(s, a->rn), imm, vsz, vsz);

    }

    return true;

}



static bool trans_AND_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn)

{

    return do_zz_dbm(s, a, tcg_gen_gvec_andi);

}



static bool trans_ORR_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn)

{

    return do_zz_dbm(s, a, tcg_gen_gvec_ori);

}



static bool trans_EOR_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn)

{

    return do_zz_dbm(s, a, tcg_gen_gvec_xori);

}



static bool trans_DUPM(DisasContext *s, arg_DUPM *a, uint32_t insn)

{

    uint64_t imm;

    if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1),

                                extract32(a->dbm, 0, 6),

                                extract32(a->dbm, 6, 6))) {

        return false;

    }

    if (sve_access_check(s)) {

        do_dupi_z(s, a->rd, imm);

    }

    return true;

}



/*

 *** SVE Memory - 32-bit Gather and Unsized Contiguous Group

 */