Commit e192becd authored by Michael Davidsaver's avatar Michael Davidsaver Committed by Peter Maydell
Browse files

armv7-m: Implement SYSRESETREQ 



Implement the SYSRESETREQ bit of the AIRCR register
for armv7-m (ie. cortex-m3) to trigger a GPIO out.

Signed-off-by: default avatarMichael Davidsaver <mdavidsaver@gmail.com>
Reviewed-by: default avatarPeter Crosthwaite <crosthwaite.peter@gmail.com>
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 20c59c38

hw/intc/armv7m_nvic.c

+8 −1
Original line number Original line Diff line number Diff line
@@ -28,6 +28,7 @@ typedef struct { 
    MemoryRegion gic_iomem_alias;

    MemoryRegion gic_iomem_alias;

    MemoryRegion container;

    MemoryRegion container;

    uint32_t num_irq;

    uint32_t num_irq;

    qemu_irq sysresetreq;

} nvic_state;

} nvic_state;





#define TYPE_NVIC "armv7m_nvic"

#define TYPE_NVIC "armv7m_nvic"
@@ -348,10 +349,13 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) 
        break;

        break;

    case 0xd0c: /* Application Interrupt/Reset Control.  */

    case 0xd0c: /* Application Interrupt/Reset Control.  */

        if ((value >> 16) == 0x05fa) {

        if ((value >> 16) == 0x05fa) {

            if (value & 4) {

                qemu_irq_pulse(s->sysresetreq);

            }

            if (value & 2) {

            if (value & 2) {

                qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n");

                qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n");

            }

            }

            if (value & 5) {

            if (value & 1) {

                qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n");

                qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n");

            }

            }

            if (value & 0x700) {

            if (value & 0x700) {
@@ -535,11 +539,14 @@ static void armv7m_nvic_instance_init(Object *obj) 
     * value in the GICState struct.

     * value in the GICState struct.

     */

     */

    GICState *s = ARM_GIC_COMMON(obj);

    GICState *s = ARM_GIC_COMMON(obj);

    DeviceState *dev = DEVICE(obj);

    nvic_state *nvic = NVIC(obj);

    /* The ARM v7m may have anything from 0 to 496 external interrupt

    /* The ARM v7m may have anything from 0 to 496 external interrupt

     * IRQ lines. We default to 64. Other boards may differ and should

     * IRQ lines. We default to 64. Other boards may differ and should

     * set the num-irq property appropriately.

     * set the num-irq property appropriately.

     */

     */

    s->num_irq = 64;

    s->num_irq = 64;

    qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);

}

}





static void armv7m_nvic_class_init(ObjectClass *klass, void *data)

static void armv7m_nvic_class_init(ObjectClass *klass, void *data)