Commit e141ab52 authored by Blue Swirl's avatar Blue Swirl
Browse files

softmmu templates: optionally pass CPUState to memory access functions 



Optionally, make memory access helpers take a parameter for CPUState
instead of relying on global env.

On most targets, perform simple moves to reorder registers. On i386,
switch from regparm(3) calling convention to standard stack-based
version.

Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
parent 6a18ae2d

cpu-all.h

+9 −0
Original line number Diff line number Diff line
@@ -259,12 +259,21 @@ extern unsigned long reserved_va; 
#define stfl(p, v) stfl_raw(p, v)

#define stfq(p, v) stfq_raw(p, v)



#ifndef CONFIG_TCG_PASS_AREG0

#define ldub_code(p) ldub_raw(p)

#define ldsb_code(p) ldsb_raw(p)

#define lduw_code(p) lduw_raw(p)

#define ldsw_code(p) ldsw_raw(p)

#define ldl_code(p) ldl_raw(p)

#define ldq_code(p) ldq_raw(p)

#else

#define cpu_ldub_code(env1, p) ldub_raw(p)

#define cpu_ldsb_code(env1, p) ldsb_raw(p)

#define cpu_lduw_code(env1, p) lduw_raw(p)

#define cpu_ldsw_code(env1, p) ldsw_raw(p)

#define cpu_ldl_code(env1, p) ldl_raw(p)

#define cpu_ldq_code(env1, p) ldq_raw(p)

#endif



#define ldub_kernel(p) ldub_raw(p)

#define ldsb_kernel(p) ldsb_raw(p)

exec-all.h

+2 −0
Original line number Diff line number Diff line
@@ -312,7 +312,9 @@ void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx, 


#define ACCESS_TYPE (NB_MMU_MODES + 1)

#define MEMSUFFIX _code

#ifndef CONFIG_TCG_PASS_AREG0

#define env cpu_single_env

#endif



#define DATA_SIZE 1

#include "softmmu_header.h"

exec.c

+4 −0
Original line number Diff line number Diff line
@@ -4595,7 +4595,11 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) 
    mmu_idx = cpu_mmu_index(env1);

    if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=

                 (addr & TARGET_PAGE_MASK))) {

#ifdef CONFIG_TCG_PASS_AREG0

        cpu_ldub_code(env1, addr);

#else

        ldub_code(addr);

#endif

    }

    pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;

    mr = iotlb_to_region(pd);

softmmu_defs.h

+28 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#ifndef SOFTMMU_DEFS_H

#define SOFTMMU_DEFS_H



#ifndef CONFIG_TCG_PASS_AREG0

uint8_t __ldb_mmu(target_ulong addr, int mmu_idx);

void __stb_mmu(target_ulong addr, uint8_t val, int mmu_idx);

uint16_t __ldw_mmu(target_ulong addr, int mmu_idx);
@@ -26,5 +27,32 @@ uint32_t __ldl_cmmu(target_ulong addr, int mmu_idx); 
void __stl_cmmu(target_ulong addr, uint32_t val, int mmu_idx);

uint64_t __ldq_cmmu(target_ulong addr, int mmu_idx);

void __stq_cmmu(target_ulong addr, uint64_t val, int mmu_idx);

#else

uint8_t helper_ldb_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);

void helper_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,

                    int mmu_idx);

uint16_t helper_ldw_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);

void helper_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,

                    int mmu_idx);

uint32_t helper_ldl_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);

void helper_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,

                    int mmu_idx);

uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);

void helper_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,

                    int mmu_idx);



uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);

void helper_stb_cmmu(CPUArchState *env, target_ulong addr, uint8_t val,

int mmu_idx);

uint16_t helper_ldw_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);

void helper_stw_cmmu(CPUArchState *env, target_ulong addr, uint16_t val,

                     int mmu_idx);

uint32_t helper_ldl_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);

void helper_stl_cmmu(CPUArchState *env, target_ulong addr, uint32_t val,

                     int mmu_idx);

uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);

void helper_stq_cmmu(CPUArchState *env, target_ulong addr, uint64_t val,

                     int mmu_idx);

#endif



#endif

softmmu_header.h

+46 −14
Original line number Diff line number Diff line
@@ -78,9 +78,23 @@ 
#define ADDR_READ addr_read

#endif



#ifndef CONFIG_TCG_PASS_AREG0

#define ENV_PARAM

#define ENV_VAR

#define CPU_PREFIX

#define HELPER_PREFIX __

#else

#define ENV_PARAM CPUArchState *env,

#define ENV_VAR env,

#define CPU_PREFIX cpu_

#define HELPER_PREFIX helper_

#endif



/* generic load/store macros */



static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)

static inline RES_TYPE

glue(glue(glue(CPU_PREFIX, ld), USUFFIX), MEMSUFFIX)(ENV_PARAM

                                                     target_ulong ptr)

{

    int page_index;

    RES_TYPE res;
@@ -93,7 +107,9 @@ static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr) 
    mmu_idx = CPU_MMU_INDEX;

    if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=

                 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {

        res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);

        res = glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_VAR

                                                                     addr,

                                                                     mmu_idx);

    } else {

        physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;

        res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
@@ -102,7 +118,9 @@ static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr) 
}



#if DATA_SIZE <= 2

static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)

static inline int

glue(glue(glue(CPU_PREFIX, lds), SUFFIX), MEMSUFFIX)(ENV_PARAM

                                                     target_ulong ptr)

{

    int res, page_index;

    target_ulong addr;
@@ -114,7 +132,8 @@ static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr) 
    mmu_idx = CPU_MMU_INDEX;

    if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=

                 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {

        res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);

        res = (DATA_STYPE)glue(glue(glue(HELPER_PREFIX, ld), SUFFIX),

                               MMUSUFFIX)(ENV_VAR addr, mmu_idx);

    } else {

        physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;

        res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
@@ -127,7 +146,9 @@ static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr) 


/* generic store macro */



static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)

static inline void

glue(glue(glue(CPU_PREFIX, st), SUFFIX), MEMSUFFIX)(ENV_PARAM target_ulong ptr,

                                                    RES_TYPE v)

{

    int page_index;

    target_ulong addr;
@@ -139,7 +160,8 @@ static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE 
    mmu_idx = CPU_MMU_INDEX;

    if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=

                 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {

        glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);

        glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_VAR addr, v,

                                                               mmu_idx);

    } else {

        physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;

        glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
@@ -151,46 +173,52 @@ static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE 
#if ACCESS_TYPE != (NB_MMU_MODES + 1)



#if DATA_SIZE == 8

static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)

static inline float64 glue(glue(CPU_PREFIX, ldfq), MEMSUFFIX)(ENV_PARAM

                                                              target_ulong ptr)

{

    union {

        float64 d;

        uint64_t i;

    } u;

    u.i = glue(ldq, MEMSUFFIX)(ptr);

    u.i = glue(glue(CPU_PREFIX, ldq), MEMSUFFIX)(ENV_VAR ptr);

    return u.d;

}



static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)

static inline void glue(glue(CPU_PREFIX, stfq), MEMSUFFIX)(ENV_PARAM

                                                           target_ulong ptr,

                                                           float64 v)

{

    union {

        float64 d;

        uint64_t i;

    } u;

    u.d = v;

    glue(stq, MEMSUFFIX)(ptr, u.i);

    glue(glue(CPU_PREFIX, stq), MEMSUFFIX)(ENV_VAR ptr, u.i);

}

#endif /* DATA_SIZE == 8 */



#if DATA_SIZE == 4

static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)

static inline float32 glue(glue(CPU_PREFIX, ldfl), MEMSUFFIX)(ENV_PARAM

                                                              target_ulong ptr)

{

    union {

        float32 f;

        uint32_t i;

    } u;

    u.i = glue(ldl, MEMSUFFIX)(ptr);

    u.i = glue(glue(CPU_PREFIX, ldl), MEMSUFFIX)(ENV_VAR ptr);

    return u.f;

}



static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)

static inline void glue(glue(CPU_PREFIX, stfl), MEMSUFFIX)(ENV_PARAM

                                                           target_ulong ptr,

                                                           float32 v)

{

    union {

        float32 f;

        uint32_t i;

    } u;

    u.f = v;

    glue(stl, MEMSUFFIX)(ptr, u.i);

    glue(glue(CPU_PREFIX, stl), MEMSUFFIX)(ENV_VAR ptr, u.i);

}

#endif /* DATA_SIZE == 4 */
@@ -205,3 +233,7 @@ static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v) 
#undef CPU_MMU_INDEX

#undef MMUSUFFIX

#undef ADDR_READ

#undef ENV_PARAM

#undef ENV_VAR

#undef CPU_PREFIX

#undef HELPER_PREFIX