Commit e13886e3 authored by Peter Maydell's avatar Peter Maydell
Browse files

armv7m: Raise correct kind of UsageFault for attempts to execute ARM code 



M profile doesn't implement ARM, and the architecturally required
behaviour for attempts to execute with the Thumb bit clear is to
generate a UsageFault with the CFSR INVSTATE bit set.  We were
incorrectly implementing this as generating an UNDEFINSTR UsageFault;
fix this.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
parent aa488fe3

linux-user/main.c

+1 −0
Original line number Diff line number Diff line
@@ -574,6 +574,7 @@ void cpu_loop(CPUARMState *env) 
        switch(trapnr) {

        case EXCP_UDEF:

        case EXCP_NOCP:

        case EXCP_INVSTATE:

            {

                TaskState *ts = cs->opaque;

                uint32_t opcode;

target/arm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ 
#define EXCP_VFIQ           15

#define EXCP_SEMIHOST       16   /* semihosting call */

#define EXCP_NOCP           17   /* v7M NOCP UsageFault */

#define EXCP_INVSTATE       18   /* v7M INVSTATE UsageFault */



#define ARMV7M_EXCP_RESET   1

#define ARMV7M_EXCP_NMI     2

target/arm/helper.c

+4 −0
Original line number Diff line number Diff line
@@ -6245,6 +6245,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) 
        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);

        env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK;

        break;

    case EXCP_INVSTATE:

        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);

        env->v7m.cfsr |= R_V7M_CFSR_INVSTATE_MASK;

        break;

    case EXCP_SWI:

        /* The PC already points to the next instruction.  */

        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);

target/arm/translate.c

+6 −2
Original line number Diff line number Diff line
@@ -7990,9 +7990,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) 
    TCGv_i32 addr;

    TCGv_i64 tmp64;



    /* M variants do not implement ARM mode.  */

    /* M variants do not implement ARM mode; this must raise the INVSTATE

     * UsageFault exception.

     */

    if (arm_dc_feature(s, ARM_FEATURE_M)) {

        goto illegal_op;

        gen_exception_insn(s, 4, EXCP_INVSTATE, syn_uncategorized(),

                           default_exception_el(s));

        return;

    }

    cond = insn >> 28;

    if (cond == 0xf){