Commit e0e367ba authored by Aurelien Jarno's avatar Aurelien Jarno
Browse files

Merge branch 'tcg-ppc64' of git://github.com/rth7680/qemu 

* 'tcg-ppc64' of git://github.com/rth7680/qemu: (33 commits)
  tcg-ppc64: Handle deposit of zero
  tcg-ppc64: Implement mulu2/muls2_i64
  tcg-ppc64: Implement add2/sub2_i64
  tcg-ppc64: Use getauxval for ISA detection
  tcg-ppc64: Implement movcond
  tcg-ppc64: Use ISEL for setcond
  tcg-ppc64: Use MFOCRF instead of MFCR
  tcg-ppc64: Cleanup i32 constants to tcg_out_cmp
  tcg-ppc64: Use TCGType throughout compares
  tcg-ppc64: Use I constraint for mul
  tcg-ppc64: Implement deposit
  tcg-ppc64: Handle constant inputs for some compound logicals
  tcg-ppc64: Implement compound logicals
  tcg-ppc64: Implement bswap64
  tcg-ppc64: Implement bswap16 and bswap32
  tcg-ppc64: Implement rotates
  tcg-ppc64: Streamline qemu_ld/st insn selection
  tcg-ppc64: Use automatic implementation of ext32u_i64
  tcg-ppc64: Improve and_i64 with constant
  tcg-ppc64: Improve and_i32 with constant
  ...
parents e6b63677 39dc85b9

configure

+18 −0
Original line number Diff line number Diff line
@@ -3308,6 +3308,20 @@ if compile_prog "" "" ; then 
    int128=yes

fi



########################################

# check if getauxval is available.



getauxval=no

cat > $TMPC << EOF

#include <sys/auxv.h>

int main(void) {

  return getauxval(AT_HWCAP) == 0;

}

EOF

if compile_prog "" "" ; then

    getauxval=yes

fi



##########################################

# End of CC checks

# After here, no more $cc or $ld runs
@@ -3858,6 +3872,10 @@ if test "$int128" = "yes" ; then 
  echo "CONFIG_INT128=y" >> $config_host_mak

fi



if test "$getauxval" = "yes" ; then

  echo "CONFIG_GETAUXVAL=y" >> $config_host_mak

fi



if test "$glusterfs" = "yes" ; then

  echo "CONFIG_GLUSTERFS=y" >> $config_host_mak

fi

disas.c

+1 −0
Original line number Diff line number Diff line
@@ -325,6 +325,7 @@ void disas(FILE *out, void *code, unsigned long size) 
    s.info.mach = bfd_mach_x86_64;

    print_insn = print_insn_i386;

#elif defined(_ARCH_PPC)

    s.info.disassembler_options = (char *)"any";

    print_insn = print_insn_ppc;

#elif defined(__alpha__)

    print_insn = print_insn_alpha;

tcg/ppc64/tcg-target.c

+917 −427

File changed.

Preview size limit exceeded, changes collapsed.

tcg/ppc64/tcg-target.h

+32 −30
Original line number Diff line number Diff line
@@ -67,53 +67,55 @@ typedef enum { 
#define TCG_TARGET_STACK_ALIGN 16

#define TCG_TARGET_CALL_STACK_OFFSET 48



/* optional instructions automatically implemented */

#define TCG_TARGET_HAS_ext8u_i32        0 /* andi */

#define TCG_TARGET_HAS_ext16u_i32       0

#define TCG_TARGET_HAS_ext8u_i64        0

#define TCG_TARGET_HAS_ext16u_i64       0

#define TCG_TARGET_HAS_ext32u_i64       0



/* optional instructions */

#define TCG_TARGET_HAS_div_i32          1

#define TCG_TARGET_HAS_rot_i32          0

#define TCG_TARGET_HAS_rot_i32          1

#define TCG_TARGET_HAS_ext8s_i32        1

#define TCG_TARGET_HAS_ext16s_i32       1

#define TCG_TARGET_HAS_ext8u_i32        0

#define TCG_TARGET_HAS_ext16u_i32       0

#define TCG_TARGET_HAS_bswap16_i32      0

#define TCG_TARGET_HAS_bswap32_i32      0

#define TCG_TARGET_HAS_bswap16_i32      1

#define TCG_TARGET_HAS_bswap32_i32      1

#define TCG_TARGET_HAS_not_i32          1

#define TCG_TARGET_HAS_neg_i32          1

#define TCG_TARGET_HAS_andc_i32         0

#define TCG_TARGET_HAS_orc_i32          0

#define TCG_TARGET_HAS_eqv_i32          0

#define TCG_TARGET_HAS_nand_i32         0

#define TCG_TARGET_HAS_nor_i32          0

#define TCG_TARGET_HAS_deposit_i32      0

#define TCG_TARGET_HAS_movcond_i32      0

#define TCG_TARGET_HAS_andc_i32         1

#define TCG_TARGET_HAS_orc_i32          1

#define TCG_TARGET_HAS_eqv_i32          1

#define TCG_TARGET_HAS_nand_i32         1

#define TCG_TARGET_HAS_nor_i32          1

#define TCG_TARGET_HAS_deposit_i32      1

#define TCG_TARGET_HAS_movcond_i32      1

#define TCG_TARGET_HAS_add2_i32         0

#define TCG_TARGET_HAS_sub2_i32         0

#define TCG_TARGET_HAS_mulu2_i32        0

#define TCG_TARGET_HAS_muls2_i32        0



#define TCG_TARGET_HAS_div_i64          1

#define TCG_TARGET_HAS_rot_i64          0

#define TCG_TARGET_HAS_rot_i64          1

#define TCG_TARGET_HAS_ext8s_i64        1

#define TCG_TARGET_HAS_ext16s_i64       1

#define TCG_TARGET_HAS_ext32s_i64       1

#define TCG_TARGET_HAS_ext8u_i64        0

#define TCG_TARGET_HAS_ext16u_i64       0

#define TCG_TARGET_HAS_ext32u_i64       1

#define TCG_TARGET_HAS_bswap16_i64      0

#define TCG_TARGET_HAS_bswap32_i64      0

#define TCG_TARGET_HAS_bswap64_i64      0

#define TCG_TARGET_HAS_bswap16_i64      1

#define TCG_TARGET_HAS_bswap32_i64      1

#define TCG_TARGET_HAS_bswap64_i64      1

#define TCG_TARGET_HAS_not_i64          1

#define TCG_TARGET_HAS_neg_i64          1

#define TCG_TARGET_HAS_andc_i64         0

#define TCG_TARGET_HAS_orc_i64          0

#define TCG_TARGET_HAS_eqv_i64          0

#define TCG_TARGET_HAS_nand_i64         0

#define TCG_TARGET_HAS_nor_i64          0

#define TCG_TARGET_HAS_deposit_i64      0

#define TCG_TARGET_HAS_movcond_i64      0

#define TCG_TARGET_HAS_add2_i64         0

#define TCG_TARGET_HAS_sub2_i64         0

#define TCG_TARGET_HAS_mulu2_i64        0

#define TCG_TARGET_HAS_muls2_i64        0

#define TCG_TARGET_HAS_andc_i64         1

#define TCG_TARGET_HAS_orc_i64          1

#define TCG_TARGET_HAS_eqv_i64          1

#define TCG_TARGET_HAS_nand_i64         1

#define TCG_TARGET_HAS_nor_i64          1

#define TCG_TARGET_HAS_deposit_i64      1

#define TCG_TARGET_HAS_movcond_i64      1

#define TCG_TARGET_HAS_add2_i64         1

#define TCG_TARGET_HAS_sub2_i64         1

#define TCG_TARGET_HAS_mulu2_i64        1

#define TCG_TARGET_HAS_muls2_i64        1



#define TCG_AREG0 TCG_REG_R27