Commit dfa9c2a0 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging 



- Migration and linuxboot fixes for 2.2 regressions
- valgrind/KVM support
- small i386 patches
- PCI SD host controller support
- malloc/free cleanups from Markus (x86/scsi)
- IvyBridge model
- XSAVES support for KVM
- initial patches from record/replay

# gpg: Signature made Mon 15 Dec 2014 16:35:08 GMT using RSA key ID 78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>"
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream: (47 commits)
  sdhci: Support SDHCI devices on PCI
  sdhci: Define SDHCI PCI ids
  sdhci: Add "sysbus" to sdhci QOM types and methods
  sdhci: Remove class "virtual" methods
  sdhci: Set a default frequency clock
  serial: only resample THR interrupt on rising edge of IER.THRI
  serial: update LSR on enabling/disabling FIFOs
  serial: clean up THRE/TEMT handling
  serial: reset thri_pending on IER writes with THRI=0
  linuxboot: fix loading old kernels
  kvm/apic: fix 2.2->2.1 migration
  target-i386: add Ivy Bridge CPU model
  target-i386: add f16c and rdrand to Haswell and Broadwell
  target-i386: add VME to all CPUs
  pc: add 2.3 machine types
  i386: do not cross the pages boundaries in replay mode
  cpus: make icount warp behave well with respect to stop/cont
  timer: introduce new QEMU_CLOCK_VIRTUAL_RT clock
  cpu-exec: invalidate nocache translation if they are interrupted
  icount: introduce cpu_get_icount_raw
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 54600752 224d10ff

cpu-exec.c

+12 −3
Original line number Diff line number Diff line
@@ -168,7 +168,9 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr) 
    }

#endif /* DEBUG_DISAS */



    cpu->can_do_io = 0;

    next_tb = tcg_qemu_tb_exec(env, tb_ptr);

    cpu->can_do_io = 1;

    trace_exec_tb_exit((void *) (next_tb & ~TB_EXIT_MASK),

                       next_tb & TB_EXIT_MASK);
@@ -202,14 +204,19 @@ static void cpu_exec_nocache(CPUArchState *env, int max_cycles, 
{

    CPUState *cpu = ENV_GET_CPU(env);

    TranslationBlock *tb;

    target_ulong pc = orig_tb->pc;

    target_ulong cs_base = orig_tb->cs_base;

    uint64_t flags = orig_tb->flags;



    /* Should never happen.

       We only end up here when an existing TB is too long.  */

    if (max_cycles > CF_COUNT_MASK)

        max_cycles = CF_COUNT_MASK;



    tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,

                     max_cycles);

    /* tb_gen_code can flush our orig_tb, invalidate it now */

    tb_phys_invalidate(orig_tb, -1);

    tb = tb_gen_code(cpu, pc, cs_base, flags,

                     max_cycles | CF_NOCACHE);

    cpu->current_tb = tb;

    /* execute the generated code */

    trace_exec_tb_nocache(tb, tb->pc);
@@ -353,7 +360,6 @@ int cpu_exec(CPUArchState *env) 
    }



    cc->cpu_exec_enter(cpu);

    cpu->exception_index = -1;



    /* Calculate difference between guest clock and host clock.

     * This delay includes the delay of the last cycle, so
@@ -373,6 +379,7 @@ int cpu_exec(CPUArchState *env) 
                    if (ret == EXCP_DEBUG) {

                        cpu_handle_debug_exception(env);

                    }

                    cpu->exception_index = -1;

                    break;

                } else {

#if defined(CONFIG_USER_ONLY)
@@ -383,6 +390,7 @@ int cpu_exec(CPUArchState *env) 
                    cc->do_interrupt(cpu);

#endif

                    ret = cpu->exception_index;

                    cpu->exception_index = -1;

                    break;

#else

                    cc->do_interrupt(cpu);
@@ -537,6 +545,7 @@ int cpu_exec(CPUArchState *env) 
            cpu = current_cpu;

            env = cpu->env_ptr;

            cc = CPU_GET_CLASS(cpu);

            cpu->can_do_io = 1;

#ifdef TARGET_I386

            x86_cpu = X86_CPU(cpu);

#endif

cpus.c

+26 −14
Original line number Diff line number Diff line
@@ -136,8 +136,7 @@ typedef struct TimersState { 


static TimersState timers_state;



/* Return the virtual CPU time, based on the instruction counter.  */

static int64_t cpu_get_icount_locked(void)

int64_t cpu_get_icount_raw(void)

{

    int64_t icount;

    CPUState *cpu = current_cpu;
@@ -145,10 +144,18 @@ static int64_t cpu_get_icount_locked(void) 
    icount = timers_state.qemu_icount;

    if (cpu) {

        if (!cpu_can_do_io(cpu)) {

            fprintf(stderr, "Bad clock read\n");

            fprintf(stderr, "Bad icount read\n");

            exit(1);

        }

        icount -= (cpu->icount_decr.u16.low + cpu->icount_extra);

    }

    return icount;

}



/* Return the virtual CPU time, based on the instruction counter.  */

static int64_t cpu_get_icount_locked(void)

{

    int64_t icount = cpu_get_icount_raw();

    return timers_state.qemu_icount_bias + cpu_icount_to_ns(icount);

}
@@ -345,7 +352,7 @@ static void icount_warp_rt(void *opaque) 


    seqlock_write_lock(&timers_state.vm_clock_seqlock);

    if (runstate_is_running()) {

        int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);

        int64_t clock = cpu_get_clock_locked();

        int64_t warp_delta;



        warp_delta = clock - vm_clock_warp_start;
@@ -354,9 +361,8 @@ static void icount_warp_rt(void *opaque) 
             * In adaptive mode, do not let QEMU_CLOCK_VIRTUAL run too

             * far ahead of real time.

             */

            int64_t cur_time = cpu_get_clock_locked();

            int64_t cur_icount = cpu_get_icount_locked();

            int64_t delta = cur_time - cur_icount;

            int64_t delta = clock - cur_icount;

            warp_delta = MIN(warp_delta, delta);

        }

        timers_state.qemu_icount_bias += warp_delta;
@@ -419,7 +425,7 @@ void qemu_clock_warp(QEMUClockType type) 
    }



    /* We want to use the earliest deadline from ALL vm_clocks */

    clock = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);

    clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);

    deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);

    if (deadline < 0) {

        return;
@@ -437,8 +443,8 @@ void qemu_clock_warp(QEMUClockType type) 
         * sleep in icount mode if there is a pending QEMU_CLOCK_VIRTUAL

         * timer; rather time could just advance to the next QEMU_CLOCK_VIRTUAL

         * event.  Instead, we do stop VCPUs and only advance QEMU_CLOCK_VIRTUAL

         * after some e"real" time, (related to the time left until the next

         * event) has passed. The QEMU_CLOCK_REALTIME timer will do this.

         * after some "real" time, (related to the time left until the next

         * event) has passed. The QEMU_CLOCK_VIRTUAL_RT clock will do this.

         * This avoids that the warps are visible externally; for example,

         * you will not be sending network packets continuously instead of

         * every 100ms.
@@ -512,7 +518,7 @@ void configure_icount(QemuOpts *opts, Error **errp) 
        return;

    }

    icount_align_option = qemu_opt_get_bool(opts, "align", false);

    icount_warp_timer = timer_new_ns(QEMU_CLOCK_REALTIME,

    icount_warp_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL_RT,

                                     icount_warp_rt, NULL);

    if (strcmp(option, "auto") != 0) {

        errno = 0;
@@ -537,10 +543,10 @@ void configure_icount(QemuOpts *opts, Error **errp) 
       the virtual time trigger catches emulated time passing too fast.

       Realtime triggers occur even when idle, so use them less frequently

       than VM triggers.  */

    icount_rt_timer = timer_new_ms(QEMU_CLOCK_REALTIME,

    icount_rt_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL_RT,

                                   icount_adjust_rt, NULL);

    timer_mod(icount_rt_timer,

                   qemu_clock_get_ms(QEMU_CLOCK_REALTIME) + 1000);

                   qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL_RT) + 1000);

    icount_vm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,

                                        icount_adjust_vm, NULL);

    timer_mod(icount_vm_timer,
@@ -934,6 +940,8 @@ static void *qemu_kvm_cpu_thread_fn(void *arg) 
    qemu_mutex_lock(&qemu_global_mutex);

    qemu_thread_get_self(cpu->thread);

    cpu->thread_id = qemu_get_thread_id();

    cpu->exception_index = -1;

    cpu->can_do_io = 1;

    current_cpu = cpu;



    r = kvm_init_vcpu(cpu);
@@ -974,6 +982,8 @@ static void *qemu_dummy_cpu_thread_fn(void *arg) 
    qemu_mutex_lock_iothread();

    qemu_thread_get_self(cpu->thread);

    cpu->thread_id = qemu_get_thread_id();

    cpu->exception_index = -1;

    cpu->can_do_io = 1;



    sigemptyset(&waitset);

    sigaddset(&waitset, SIG_IPI);
@@ -1016,6 +1026,8 @@ static void *qemu_tcg_cpu_thread_fn(void *arg) 
    CPU_FOREACH(cpu) {

        cpu->thread_id = qemu_get_thread_id();

        cpu->created = true;

        cpu->exception_index = -1;

        cpu->can_do_io = 1;

    }

    qemu_cond_signal(&qemu_cpu_cond);

default-configs/pci.mak

+2 −0
Original line number Diff line number Diff line
@@ -30,3 +30,5 @@ CONFIG_IPACK=y 
CONFIG_WDT_IB6300ESB=y

CONFIG_PCI_TESTDEV=y

CONFIG_NVME_PCI=y

CONFIG_SD=y

CONFIG_SDHCI=y

docs/specs/pci-ids.txt

+2 −0
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@ PCI devices (other than virtio): 
1b36:0002  PCI serial port (16550A) adapter (docs/specs/pci-serial.txt)

1b36:0003  PCI Dual-port 16550A adapter (docs/specs/pci-serial.txt)

1b36:0004  PCI Quad-port 16550A adapter (docs/specs/pci-serial.txt)

1b36:0005  PCI test device (docs/specs/pci-testdev.txt)

1b36:0006  PCI SD Card Host Controller Interface (SDHCI)



All these devices are documented in docs/specs.

hw/char/serial.c

+40 −18
Original line number Diff line number Diff line
@@ -224,21 +224,23 @@ static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque) 
    SerialState *s = opaque;



    do {

        assert(!(s->lsr & UART_LSR_TEMT));

        if (s->tsr_retry <= 0) {

            assert(!(s->lsr & UART_LSR_THRE));



            if (s->fcr & UART_FCR_FE) {

                if (fifo8_is_empty(&s->xmit_fifo)) {

                    return FALSE;

                }

                assert(!fifo8_is_empty(&s->xmit_fifo));

                s->tsr = fifo8_pop(&s->xmit_fifo);

                if (!s->xmit_fifo.num) {

                    s->lsr |= UART_LSR_THRE;

                }

            } else if ((s->lsr & UART_LSR_THRE)) {

                return FALSE;

            } else {

                s->tsr = s->thr;

                s->lsr |= UART_LSR_THRE;

                s->lsr &= ~UART_LSR_TEMT;

            }

            if ((s->lsr & UART_LSR_THRE) && !s->thr_ipending) {

                s->thr_ipending = 1;

                serial_update_irq(s);

            }

        }
@@ -256,17 +258,13 @@ static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque) 
        } else {

            s->tsr_retry = 0;

        }



        /* Transmit another byte if it is already available. It is only

           possible when FIFO is enabled and not empty. */

    } while ((s->fcr & UART_FCR_FE) && !fifo8_is_empty(&s->xmit_fifo));

    } while (!(s->lsr & UART_LSR_THRE));



    s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);



    if (s->lsr & UART_LSR_THRE) {

    s->lsr |= UART_LSR_TEMT;

        s->thr_ipending = 1;

        serial_update_irq(s);

    }



    return FALSE;

}
@@ -323,10 +321,10 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, 
                    fifo8_pop(&s->xmit_fifo);

                }

                fifo8_push(&s->xmit_fifo, s->thr);

                s->lsr &= ~UART_LSR_TEMT;

            }

            s->thr_ipending = 0;

            s->lsr &= ~UART_LSR_THRE;

            s->lsr &= ~UART_LSR_TEMT;

            serial_update_irq(s);

            if (s->tsr_retry <= 0) {

                serial_xmit(NULL, G_IO_OUT, s);
@@ -338,10 +336,12 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, 
            s->divider = (s->divider & 0x00ff) | (val << 8);

            serial_update_parameters(s);

        } else {

            uint8_t changed = (s->ier ^ val) & 0x0f;

            s->ier = val & 0x0f;

            /* If the backend device is a real serial port, turn polling of the modem

               status lines on physical port on or off depending on UART_IER_MSI state */

            if (s->poll_msl >= 0) {

             * status lines on physical port on or off depending on UART_IER_MSI state.

             */

            if ((changed & UART_IER_MSI) && s->poll_msl >= 0) {

                if (s->ier & UART_IER_MSI) {

                     s->poll_msl = 1;

                     serial_update_msl(s);
@@ -350,8 +350,27 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, 
                     s->poll_msl = 0;

                }

            }

            if (s->lsr & UART_LSR_THRE) {



            /* Turning on the THRE interrupt on IER can trigger the interrupt

             * if LSR.THRE=1, even if it had been masked before by reading IIR.

             * This is not in the datasheet, but Windows relies on it.  It is

             * unclear if THRE has to be resampled every time THRI becomes

             * 1, or only on the rising edge.  Bochs does the latter, and Windows

             * always toggles IER to all zeroes and back to all ones, so do the

             * same.

             *

             * If IER.THRI is zero, thr_ipending is not used.  Set it to zero

             * so that the thr_ipending subsection is not migrated.

             */

            if (changed & UART_IER_THRI) {

                if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) {

                    s->thr_ipending = 1;

                } else {

                    s->thr_ipending = 0;

                }

            }



            if (changed) {

                serial_update_irq(s);

            }

        }
@@ -365,12 +384,15 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, 
        /* FIFO clear */



        if (val & UART_FCR_RFR) {

            s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);

            timer_del(s->fifo_timeout_timer);

            s->timeout_ipending = 0;

            fifo8_reset(&s->recv_fifo);

        }



        if (val & UART_FCR_XFR) {

            s->lsr |= UART_LSR_THRE;

            s->thr_ipending = 1;

            fifo8_reset(&s->xmit_fifo);

        }