Commit df6606f4 authored by Anthony Liguori's avatar Anthony Liguori
Browse files

Merge remote-tracking branch 'mst/tags/for_anthony' into staging 

* mst/tags/for_anthony:
  pci_bridge_dev: fix error path in pci_bridge_dev_initfn()
  qdev: release parent properties on dc->init failure
  msi: Use msi/msix_present more consistently
  msi: Invoke msi/msix_write_config from PCI core
  msi: Guard msi/msix_write_config with msi_present
  msi: Invoke msi/msix_reset from PCI core
  msi: Guard msi_reset with msi_present
  ahci: Clean up reset functions
  intel-hda: Fix reset of MSI function
  ahci: Fix reset of MSI function
  rtl8139: honor RxOverflow flag in can_receive method
  shpc: unparent device before free
parents 49023ff7 80aa796b

hw/ide/ahci.c

+15 −10
Original line number Diff line number Diff line
@@ -339,7 +339,7 @@ static void ahci_mem_write(void *opaque, target_phys_addr_t addr, 
            case HOST_CTL: /* R/W */

                if (val & HOST_CTL_RESET) {

                    DPRINTF(-1, "HBA Reset\n");

                    ahci_reset(container_of(s, AHCIPCIState, ahci));

                    ahci_reset(s);

                } else {

                    s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;

                    ahci_check_irq(s);
@@ -1149,21 +1149,20 @@ void ahci_uninit(AHCIState *s) 
    g_free(s->dev);

}



void ahci_reset(void *opaque)

void ahci_reset(AHCIState *s)

{

    struct AHCIPCIState *d = opaque;

    AHCIPortRegs *pr;

    int i;



    d->ahci.control_regs.irqstatus = 0;

    d->ahci.control_regs.ghc = 0;

    s->control_regs.irqstatus = 0;

    s->control_regs.ghc = 0;



    for (i = 0; i < d->ahci.ports; i++) {

        pr = &d->ahci.dev[i].port_regs;

    for (i = 0; i < s->ports; i++) {

        pr = &s->dev[i].port_regs;

        pr->irq_stat = 0;

        pr->irq_mask = 0;

        pr->scr_ctl = 0;

        ahci_reset_port(&d->ahci, i);

        ahci_reset_port(s, i);

    }

}
@@ -1178,6 +1177,13 @@ static const VMStateDescription vmstate_sysbus_ahci = { 
    .unmigratable = 1,

};



static void sysbus_ahci_reset(DeviceState *dev)

{

    SysbusAHCIState *s = DO_UPCAST(SysbusAHCIState, busdev.qdev, dev);



    ahci_reset(&s->ahci);

}



static int sysbus_ahci_init(SysBusDevice *dev)

{

    SysbusAHCIState *s = FROM_SYSBUS(SysbusAHCIState, dev);
@@ -1185,8 +1191,6 @@ static int sysbus_ahci_init(SysBusDevice *dev) 


    sysbus_init_mmio(dev, &s->ahci.mem);

    sysbus_init_irq(dev, &s->ahci.irq);



    qemu_register_reset(ahci_reset, &s->ahci);

    return 0;

}
@@ -1203,6 +1207,7 @@ static void sysbus_ahci_class_init(ObjectClass *klass, void *data) 
    sbc->init = sysbus_ahci_init;

    dc->vmsd = &vmstate_sysbus_ahci;

    dc->props = sysbus_ahci_properties;

    dc->reset = sysbus_ahci_reset;

}



static TypeInfo sysbus_ahci_info = {

hw/ide/ahci.h

+1 −1
Original line number Diff line number Diff line
@@ -332,6 +332,6 @@ typedef struct NCQFrame { 
void ahci_init(AHCIState *s, DeviceState *qdev, int ports);

void ahci_uninit(AHCIState *s);



void ahci_reset(void *opaque);

void ahci_reset(AHCIState *s);



#endif /* HW_IDE_AHCI_H */

hw/ide/ich.c

+8 −11
Original line number Diff line number Diff line
@@ -84,6 +84,13 @@ static const VMStateDescription vmstate_ahci = { 
    .unmigratable = 1,

};



static void pci_ich9_reset(DeviceState *dev)

{

    struct AHCIPCIState *d = DO_UPCAST(struct AHCIPCIState, card.qdev, dev);



    ahci_reset(&d->ahci);

}



static int pci_ich9_ahci_init(PCIDevice *dev)

{

    struct AHCIPCIState *d;
@@ -102,8 +109,6 @@ static int pci_ich9_ahci_init(PCIDevice *dev) 
    /* XXX Software should program this register */

    d->card.config[0x90]   = 1 << 6; /* Address Map Register - AHCI mode */



    qemu_register_reset(ahci_reset, d);



    msi_init(dev, 0x50, 1, true, false);

    d->ahci.irq = d->card.irq[0];
@@ -133,19 +138,11 @@ static int pci_ich9_uninit(PCIDevice *dev) 
    d = DO_UPCAST(struct AHCIPCIState, card, dev);



    msi_uninit(dev);

    qemu_unregister_reset(ahci_reset, d);

    ahci_uninit(&d->ahci);



    return 0;

}



static void pci_ich9_write_config(PCIDevice *pci, uint32_t addr,

                                  uint32_t val, int len)

{

    pci_default_write_config(pci, addr, val, len);

    msi_write_config(pci, addr, val, len);

}



static void ich_ahci_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);
@@ -153,12 +150,12 @@ static void ich_ahci_class_init(ObjectClass *klass, void *data) 


    k->init = pci_ich9_ahci_init;

    k->exit = pci_ich9_uninit;

    k->config_write = pci_ich9_write_config;

    k->vendor_id = PCI_VENDOR_ID_INTEL;

    k->device_id = PCI_DEVICE_ID_INTEL_82801IR;

    k->revision = 0x02;

    k->class_id = PCI_CLASS_STORAGE_SATA;

    dc->vmsd = &vmstate_ahci;

    dc->reset = pci_ich9_reset;

}



static TypeInfo ich_ahci_info = {

hw/intel-hda.c

+0 −12
Original line number Diff line number Diff line
@@ -1153,17 +1153,6 @@ static int intel_hda_exit(PCIDevice *pci) 
    return 0;

}



static void intel_hda_write_config(PCIDevice *pci, uint32_t addr,

                                   uint32_t val, int len)

{

    IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);



    pci_default_write_config(pci, addr, val, len);

    if (d->msi) {

        msi_write_config(pci, addr, val, len);

    }

}



static int intel_hda_post_load(void *opaque, int version)

{

    IntelHDAState* d = opaque;
@@ -1252,7 +1241,6 @@ static void intel_hda_class_init(ObjectClass *klass, void *data) 


    k->init = intel_hda_init;

    k->exit = intel_hda_exit;

    k->config_write = intel_hda_write_config;

    k->vendor_id = PCI_VENDOR_ID_INTEL;

    k->device_id = 0x2668;

    k->revision = 1;

hw/ioh3420.c

+1 −2
Original line number Diff line number Diff line
@@ -71,7 +71,6 @@ static void ioh3420_write_config(PCIDevice *d, 
        pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);



    pci_bridge_write_config(d, address, val, len);

    msi_write_config(d, address, val, len);

    ioh3420_aer_vector_update(d);

    pcie_cap_slot_write_config(d, address, val, len);

    pcie_aer_write_config(d, address, val, len);
@@ -81,7 +80,7 @@ static void ioh3420_write_config(PCIDevice *d, 
static void ioh3420_reset(DeviceState *qdev)

{

    PCIDevice *d = PCI_DEVICE(qdev);

    msi_reset(d);



    ioh3420_aer_vector_update(d);

    pcie_cap_root_reset(d);

    pcie_cap_deverr_reset(d);