Unverified Commit df354dd4 authored by Michael Clark's avatar Michael Clark Committed by Palmer Dabbelt
Browse files

RISC-V: Move non-ops from op_helper to cpu_helper 



This patch makes op_helper.c contain only instruction
operation helpers used by translate.c and moves any
unrelated cpu helpers into cpu_helper.c. No logic is
changed by this patch.

Signed-off-by: default avatarMichael Clark <mjc@sifive.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: default avatarPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 85ba724f

target/riscv/Makefile.objs

+1 −1
Original line number Diff line number Diff line 
obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o gdbstub.o pmp.o
 
obj-y += translate.o op_helper.o cpu_helper.o cpu.o fpu_helper.o gdbstub.o pmp.o

target/riscv/helper.c→target/riscv/cpu_helper.c

+34 −1
Original line number Diff line number Diff line 
/*

 * RISC-V emulation helpers for qemu.

 * RISC-V CPU helpers for qemu.

 *

 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu

 * Copyright (c) 2017-2018 SiFive, Inc.
@@ -72,6 +72,39 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 


#if !defined(CONFIG_USER_ONLY)



/* iothread_mutex must be held */

uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)

{

    CPURISCVState *env = &cpu->env;

    uint32_t old, new, cmp = atomic_read(&env->mip);



    do {

        old = cmp;

        new = (old & ~mask) | (value & mask);

        cmp = atomic_cmpxchg(&env->mip, old, new);

    } while (old != cmp);



    if (new && !old) {

        cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);

    } else if (!new && old) {

        cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);

    }



    return old;

}



void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)

{

    if (newpriv > PRV_M) {

        g_assert_not_reached();

    }

    if (newpriv == PRV_H) {

        newpriv = PRV_U;

    }

    /* tlb_flush is unnecessary as mode is contained in mmu_idx */

    env->priv = newpriv;

}



/* get_physical_address - get the physical address for this virtual address

 *

 * Do a page table walk to obtain the physical address corresponding to a

target/riscv/op_helper.c

+0 −34
Original line number Diff line number Diff line
@@ -654,39 +654,6 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src, 


#ifndef CONFIG_USER_ONLY



/* iothread_mutex must be held */

uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)

{

    CPURISCVState *env = &cpu->env;

    uint32_t old, new, cmp = atomic_read(&env->mip);



    do {

        old = cmp;

        new = (old & ~mask) | (value & mask);

        cmp = atomic_cmpxchg(&env->mip, old, new);

    } while (old != cmp);



    if (new && !old) {

        cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);

    } else if (!new && old) {

        cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);

    }



    return old;

}



void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)

{

    if (newpriv > PRV_M) {

        g_assert_not_reached();

    }

    if (newpriv == PRV_H) {

        newpriv = PRV_U;

    }

    /* tlb_flush is unnecessary as mode is contained in mmu_idx */

    env->priv = newpriv;

}



target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)

{

    if (!(env->priv >= PRV_S)) {
@@ -737,7 +704,6 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) 
    return retpc;

}





void helper_wfi(CPURISCVState *env)

{

    CPUState *cs = CPU(riscv_env_get_cpu(env));