Loading target/s390x/helper.h +1 −0 Original line number Diff line number Diff line Loading @@ -204,6 +204,7 @@ DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) DEF_HELPER_FLAGS_4(gvec_verim8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) DEF_HELPER_FLAGS_4(gvec_verim16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) #ifndef CONFIG_USER_ONLY DEF_HELPER_3(servc, i32, env, i64, i64) Loading target/s390x/insn-data.def +4 −0 Original line number Diff line number Diff line Loading @@ -1160,6 +1160,10 @@ /* VECTOR ELEMENT SHIFT RIGHT LOGICAL */ F(0xe778, VESRLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC) F(0xe738, VESRL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC) /* VECTOR SHIFT LEFT */ F(0xe774, VSL, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC) /* VECTOR SHIFT LEFT BY BYTE */ F(0xe775, VSLB, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC) #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ Loading target/s390x/translate_vx.inc.c +20 −0 Original line number Diff line number Diff line Loading @@ -188,6 +188,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr, #define gen_gvec_2s(v1, v2, c, gen) \ tcg_gen_gvec_2s(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ 16, 16, c, gen) #define gen_gvec_2i_ool(v1, v2, c, data, fn) \ tcg_gen_gvec_2i_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ c, 16, 16, data, fn) #define gen_gvec_3(v1, v2, v3, gen) \ tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ vec_full_reg_offset(v3), 16, 16, gen) Loading Loading @@ -2040,3 +2043,20 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o) } return DISAS_NEXT; } static DisasJumpType op_vsl(DisasContext *s, DisasOps *o) { TCGv_i64 shift = tcg_temp_new_i64(); read_vec_element_i64(shift, get_field(s->fields, v3), 7, ES_8); if (s->fields->op2 == 0x74) { tcg_gen_andi_i64(shift, shift, 0x7); } else { tcg_gen_andi_i64(shift, shift, 0x78); } gen_gvec_2i_ool(get_field(s->fields, v1), get_field(s->fields, v2), shift, 0, gen_helper_gvec_vsl); tcg_temp_free_i64(shift); return DISAS_NEXT; } target/s390x/vec_int_helper.c +6 −0 Original line number Diff line number Diff line Loading @@ -529,3 +529,9 @@ void HELPER(gvec_verim##BITS)(void *v1, const void *v2, const void *v3, \ } DEF_VERIM(8) DEF_VERIM(16) void HELPER(gvec_vsl)(void *v1, const void *v2, uint64_t count, uint32_t desc) { s390_vec_shl(v1, v2, count); } Loading
target/s390x/helper.h +1 −0 Original line number Diff line number Diff line Loading @@ -204,6 +204,7 @@ DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) DEF_HELPER_FLAGS_4(gvec_verim8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) DEF_HELPER_FLAGS_4(gvec_verim16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) #ifndef CONFIG_USER_ONLY DEF_HELPER_3(servc, i32, env, i64, i64) Loading
target/s390x/insn-data.def +4 −0 Original line number Diff line number Diff line Loading @@ -1160,6 +1160,10 @@ /* VECTOR ELEMENT SHIFT RIGHT LOGICAL */ F(0xe778, VESRLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC) F(0xe738, VESRL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC) /* VECTOR SHIFT LEFT */ F(0xe774, VSL, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC) /* VECTOR SHIFT LEFT BY BYTE */ F(0xe775, VSLB, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC) #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ Loading
target/s390x/translate_vx.inc.c +20 −0 Original line number Diff line number Diff line Loading @@ -188,6 +188,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr, #define gen_gvec_2s(v1, v2, c, gen) \ tcg_gen_gvec_2s(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ 16, 16, c, gen) #define gen_gvec_2i_ool(v1, v2, c, data, fn) \ tcg_gen_gvec_2i_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ c, 16, 16, data, fn) #define gen_gvec_3(v1, v2, v3, gen) \ tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ vec_full_reg_offset(v3), 16, 16, gen) Loading Loading @@ -2040,3 +2043,20 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o) } return DISAS_NEXT; } static DisasJumpType op_vsl(DisasContext *s, DisasOps *o) { TCGv_i64 shift = tcg_temp_new_i64(); read_vec_element_i64(shift, get_field(s->fields, v3), 7, ES_8); if (s->fields->op2 == 0x74) { tcg_gen_andi_i64(shift, shift, 0x7); } else { tcg_gen_andi_i64(shift, shift, 0x78); } gen_gvec_2i_ool(get_field(s->fields, v1), get_field(s->fields, v2), shift, 0, gen_helper_gvec_vsl); tcg_temp_free_i64(shift); return DISAS_NEXT; }
target/s390x/vec_int_helper.c +6 −0 Original line number Diff line number Diff line Loading @@ -529,3 +529,9 @@ void HELPER(gvec_verim##BITS)(void *v1, const void *v2, const void *v3, \ } DEF_VERIM(8) DEF_VERIM(16) void HELPER(gvec_vsl)(void *v1, const void *v2, uint64_t count, uint32_t desc) { s390_vec_shl(v1, v2, count); }