Loading cpu-exec.c +0 −32 Original line number Diff line number Diff line Loading @@ -597,38 +597,6 @@ int cpu_exec(CPUArchState *env) cc->do_interrupt(cpu); next_tb = 0; } #elif defined(TARGET_ALPHA) { int idx = -1; /* ??? This hard-codes the OSF/1 interrupt levels. */ switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) { case 0 ... 3: if (interrupt_request & CPU_INTERRUPT_HARD) { idx = EXCP_DEV_INTERRUPT; } /* FALLTHRU */ case 4: if (interrupt_request & CPU_INTERRUPT_TIMER) { idx = EXCP_CLK_INTERRUPT; } /* FALLTHRU */ case 5: if (interrupt_request & CPU_INTERRUPT_SMP) { idx = EXCP_SMP_INTERRUPT; } /* FALLTHRU */ case 6: if (interrupt_request & CPU_INTERRUPT_MCHK) { idx = EXCP_MCHK; } } if (idx >= 0) { cpu->exception_index = idx; env->error_code = 0; cc->do_interrupt(cpu); next_tb = 0; } } #endif /* The target hook has 3 exit conditions: False when the interrupt isn't processed, Loading target-alpha/cpu-qom.h +1 −0 Original line number Diff line number Diff line Loading @@ -79,6 +79,7 @@ extern const struct VMStateDescription vmstate_alpha_cpu; #endif void alpha_cpu_do_interrupt(CPUState *cpu); bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); Loading target-alpha/cpu.c +1 −0 Original line number Diff line number Diff line Loading @@ -284,6 +284,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = alpha_cpu_class_by_name; cc->has_work = alpha_cpu_has_work; cc->do_interrupt = alpha_cpu_do_interrupt; cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt; cc->dump_state = alpha_cpu_dump_state; cc->set_pc = alpha_cpu_set_pc; cc->gdb_read_register = alpha_cpu_gdb_read_register; Loading target-alpha/helper.c +44 −0 Original line number Diff line number Diff line Loading @@ -470,6 +470,50 @@ void alpha_cpu_do_interrupt(CPUState *cs) #endif /* !USER_ONLY */ } bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { AlphaCPU *cpu = ALPHA_CPU(cs); CPUAlphaState *env = &cpu->env; int idx = -1; /* We never take interrupts while in PALmode. */ if (env->pal_mode) { return false; } /* Fall through the switch, collecting the highest priority interrupt that isn't masked by the processor status IPL. */ /* ??? This hard-codes the OSF/1 interrupt levels. */ switch (env->ps & PS_INT_MASK) { case 0 ... 3: if (interrupt_request & CPU_INTERRUPT_HARD) { idx = EXCP_DEV_INTERRUPT; } /* FALLTHRU */ case 4: if (interrupt_request & CPU_INTERRUPT_TIMER) { idx = EXCP_CLK_INTERRUPT; } /* FALLTHRU */ case 5: if (interrupt_request & CPU_INTERRUPT_SMP) { idx = EXCP_SMP_INTERRUPT; } /* FALLTHRU */ case 6: if (interrupt_request & CPU_INTERRUPT_MCHK) { idx = EXCP_MCHK; } } if (idx >= 0) { cs->exception_index = idx; env->error_code = 0; alpha_cpu_do_interrupt(cs); return true; } return false; } void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { Loading Loading
cpu-exec.c +0 −32 Original line number Diff line number Diff line Loading @@ -597,38 +597,6 @@ int cpu_exec(CPUArchState *env) cc->do_interrupt(cpu); next_tb = 0; } #elif defined(TARGET_ALPHA) { int idx = -1; /* ??? This hard-codes the OSF/1 interrupt levels. */ switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) { case 0 ... 3: if (interrupt_request & CPU_INTERRUPT_HARD) { idx = EXCP_DEV_INTERRUPT; } /* FALLTHRU */ case 4: if (interrupt_request & CPU_INTERRUPT_TIMER) { idx = EXCP_CLK_INTERRUPT; } /* FALLTHRU */ case 5: if (interrupt_request & CPU_INTERRUPT_SMP) { idx = EXCP_SMP_INTERRUPT; } /* FALLTHRU */ case 6: if (interrupt_request & CPU_INTERRUPT_MCHK) { idx = EXCP_MCHK; } } if (idx >= 0) { cpu->exception_index = idx; env->error_code = 0; cc->do_interrupt(cpu); next_tb = 0; } } #endif /* The target hook has 3 exit conditions: False when the interrupt isn't processed, Loading
target-alpha/cpu-qom.h +1 −0 Original line number Diff line number Diff line Loading @@ -79,6 +79,7 @@ extern const struct VMStateDescription vmstate_alpha_cpu; #endif void alpha_cpu_do_interrupt(CPUState *cpu); bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); Loading
target-alpha/cpu.c +1 −0 Original line number Diff line number Diff line Loading @@ -284,6 +284,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = alpha_cpu_class_by_name; cc->has_work = alpha_cpu_has_work; cc->do_interrupt = alpha_cpu_do_interrupt; cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt; cc->dump_state = alpha_cpu_dump_state; cc->set_pc = alpha_cpu_set_pc; cc->gdb_read_register = alpha_cpu_gdb_read_register; Loading
target-alpha/helper.c +44 −0 Original line number Diff line number Diff line Loading @@ -470,6 +470,50 @@ void alpha_cpu_do_interrupt(CPUState *cs) #endif /* !USER_ONLY */ } bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { AlphaCPU *cpu = ALPHA_CPU(cs); CPUAlphaState *env = &cpu->env; int idx = -1; /* We never take interrupts while in PALmode. */ if (env->pal_mode) { return false; } /* Fall through the switch, collecting the highest priority interrupt that isn't masked by the processor status IPL. */ /* ??? This hard-codes the OSF/1 interrupt levels. */ switch (env->ps & PS_INT_MASK) { case 0 ... 3: if (interrupt_request & CPU_INTERRUPT_HARD) { idx = EXCP_DEV_INTERRUPT; } /* FALLTHRU */ case 4: if (interrupt_request & CPU_INTERRUPT_TIMER) { idx = EXCP_CLK_INTERRUPT; } /* FALLTHRU */ case 5: if (interrupt_request & CPU_INTERRUPT_SMP) { idx = EXCP_SMP_INTERRUPT; } /* FALLTHRU */ case 6: if (interrupt_request & CPU_INTERRUPT_MCHK) { idx = EXCP_MCHK; } } if (idx >= 0) { cs->exception_index = idx; env->error_code = 0; alpha_cpu_do_interrupt(cs); return true; } return false; } void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { Loading