Commit dd581bf9 authored by Fredrik Noring's avatar Fredrik Noring Committed by Aleksandar Markovic
Browse files

target/mips: Define R5900 MMI3 opcode constants 



Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarFredrik Noring <noring@nocrew.org>
Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
parent 6c03ef6a

target/mips/translate.c

+39 −0
Original line number Diff line number Diff line
@@ -2323,6 +2323,45 @@ enum { 
    TX79_MMI2_PROT3W = (0x1F << 6) | TX79_MMI_CLASS_MMI2,

};









/*









 * TX79 Multimedia Instructions with opcode field = MMI and bits 5..0 = MMI3:









 *









 *  31    26                        10     6 5      0









 * +--------+----------------------+--------+--------+









 * |   MMI  |                      |function|  MMI3  |









 * +--------+----------------------+--------+--------+









 *









 * function  bits 7..6









 *     bits |   0   |   1   |   2   |   3









 *    10..8 |   00  |   01  |   10  |   11









 *   -------+-------+-------+-------+-------









 *    0 000 |PMADDUW|   *   |   *   | PSRAVW









 *    1 001 |   *   |   *   |   *   |   *









 *    2 010 | PMTHI | PMTLO | PINTEH|   *









 *    3 011 |PMULTUW| PDIVUW| PCPYUD|   *









 *    4 100 |   *   |   *   |  POR  |  PNOR









 *    5 101 |   *   |   *   |   *   |   *









 *    6 110 |   *   |   *   | PEXCH | PCPYH









 *    7 111 |   *   |   *   | PEXCW |   *









 */

















#define MASK_TX79_MMI3(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))









enum {









    TX79_MMI3_PMADDUW = (0x00 << 6) | TX79_MMI_CLASS_MMI3,









    TX79_MMI3_PSRAVW  = (0x03 << 6) | TX79_MMI_CLASS_MMI3,









    TX79_MMI3_PMTHI   = (0x08 << 6) | TX79_MMI_CLASS_MMI3,









    TX79_MMI3_PMTLO   = (0x09 << 6) | TX79_MMI_CLASS_MMI3,









    TX79_MMI3_PINTEH  = (0x0A << 6) | TX79_MMI_CLASS_MMI3,









    TX79_MMI3_PMULTUW = (0x0C << 6) | TX79_MMI_CLASS_MMI3,









    TX79_MMI3_PDIVUW  = (0x0D << 6) | TX79_MMI_CLASS_MMI3,









    TX79_MMI3_PCPYUD  = (0x0E << 6) | TX79_MMI_CLASS_MMI3,









    TX79_MMI3_POR     = (0x12 << 6) | TX79_MMI_CLASS_MMI3,









    TX79_MMI3_PNOR    = (0x13 << 6) | TX79_MMI_CLASS_MMI3,









    TX79_MMI3_PEXCH   = (0x1A << 6) | TX79_MMI_CLASS_MMI3,









    TX79_MMI3_PCPYH   = (0x1B << 6) | TX79_MMI_CLASS_MMI3,









    TX79_MMI3_PEXCW   = (0x1E << 6) | TX79_MMI_CLASS_MMI3,









};

















/* global register indices */









static TCGv cpu_gpr[32], cpu_PC;









static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];