Commit dcbd26f8 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.13-20180427' into staging 



ppc patch queue 2018-04-27

Here's the first batch of ppc patches for 2.13.  This has a lot of
stuff that's accumulated during the 2.12 freeze.  Highlights are:

    * Many improvements for the Uninorth PCI host bridge for Mac
      machine types
    * Preliminary helpers improve handling of multiple backing
      pagesizes (not strictly ppc related, but have acks and aimed to
      allow future ppc changes)
    * Cleanups to pseries cpu initialization
    * Cleanups to hash64 MMU handling
    * Assorted bugfixes and improvements

# gpg: Signature made Fri 27 Apr 2018 10:20:30 BST
# gpg:                using RSA key 6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>"
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>"
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.13-20180427: (49 commits)
  Clear mem_path if we fall back to anonymous RAM allocation
  spapr: Set compatibility mode before the rest of spapr_cpu_reset()
  target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr()
  spapr: Support ibm,dynamic-memory-v2 property
  ppc: e500: switch E500 based machines to full machine definition
  spapr: Add ibm,max-associativity-domains property
  target/ppc: Fold slb_nr into PPCHash64Options
  target/ppc: Get rid of POWERPC_MMU_VER() macros
  target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model
  target/ppc: Fold ci_large_pages flag into PPCHash64Options
  target/ppc: Move 1T segment and AMR options to PPCHash64Options
  target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs
  target/ppc: Split page size information into a separate allocation
  target/ppc: Move page size setup to helper function
  target/ppc: Remove fallback 64k pagesize information
  target/ppc: Avoid taking "env" parameter to mmu-hash64 functions
  target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop()
  target/ppc: Simplify cpu valid check in ppc_cpu_realize
  target/ppc: Standardize instance_init and realize function names
  spapr: drop useless dynamic sysbus device sanity check
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents ca926516 6233b679

backends/hostmem.c

+18 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include "qapi/visitor.h"

#include "qemu/config-file.h"

#include "qom/object_interfaces.h"

#include "qemu/mmap-alloc.h"



#ifdef CONFIG_NUMA

#include <numaif.h>
@@ -262,6 +263,23 @@ bool host_memory_backend_is_mapped(HostMemoryBackend *backend) 
    return backend->is_mapped;

}



#ifdef __linux__

size_t host_memory_backend_pagesize(HostMemoryBackend *memdev)

{

    Object *obj = OBJECT(memdev);

    char *path = object_property_get_str(obj, "mem-path", NULL);

    size_t pagesize = qemu_mempath_getpagesize(path);



    g_free(path);

    return pagesize;

}

#else

size_t host_memory_backend_pagesize(HostMemoryBackend *memdev)

{

    return getpagesize();

}

#endif



static void

host_memory_backend_memory_complete(UserCreatable *uc, Error **errp)

{

docs/specs/ppc-spapr-hotplug.txt

+19 −0
Original line number Diff line number Diff line
@@ -387,4 +387,23 @@ Each LMB list entry consists of the following elements: 
- A 32bit flags word. The bit at bit position 0x00000008 defines whether

  the LMB is assigned to the the partition as of boot time.



ibm,dynamic-memory-v2



This property describes the dynamically reconfigurable memory. This is

an alternate and newer way to describe dyanamically reconfigurable memory.

It is a property encoded array that has an integer N (the number of

LMB set entries) followed by N LMB set entries. There is an LMB set entry

for each sequential group of LMBs that share common attributes.



Each LMB set entry consists of the following elements:



- Number of sequential LMBs in the entry represented by a 32bit integer.

- Logical address of the first LMB in the set encoded as a 64bit integer.

- DRC index of the first LMB in the set.

- Associativity list index that is used as an index into

  ibm,associativity-lookup-arrays property described earlier. This

  is used to retrieve the right associativity list to be used for all

  the LMBs in this set.

- A 32bit flags word that applies to all the LMBs in the set.



[1] http://thread.gmane.org/gmane.linux.ports.ppc.embedded/75350/focus=106867

exec.c

+5 −15
Original line number Diff line number Diff line
@@ -1488,20 +1488,14 @@ void ram_block_dump(Monitor *mon) 
 */

static int find_max_supported_pagesize(Object *obj, void *opaque)

{

    char *mem_path;

    long *hpsize_min = opaque;



    if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {

        mem_path = object_property_get_str(obj, "mem-path", NULL);

        if (mem_path) {

            long hpsize = qemu_mempath_getpagesize(mem_path);

            g_free(mem_path);

        long hpsize = host_memory_backend_pagesize(MEMORY_BACKEND(obj));



        if (hpsize < *hpsize_min) {

            *hpsize_min = hpsize;

        }

        } else {

            *hpsize_min = getpagesize();

        }

    }



    return 0;
@@ -1513,11 +1507,7 @@ long qemu_getrampagesize(void) 
    long mainrampagesize;

    Object *memdev_root;



    if (mem_path) {

    mainrampagesize = qemu_mempath_getpagesize(mem_path);

    } else {

        mainrampagesize = getpagesize();

    }



    /* it's possible we have memory-backend objects with

     * hugepage-backed RAM. these may get mapped into system

hw/intc/heathrow_pic.c

+5 −18
Original line number Diff line number Diff line
@@ -172,27 +172,14 @@ static void heathrow_init(Object *obj) 
    HeathrowState *s = HEATHROW(obj);

    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);



    memory_region_init_io(&s->mem, OBJECT(s), &heathrow_ops, s,

                          "heathrow-pic", 0x1000);

    sysbus_init_mmio(sbd, &s->mem);

}



DeviceState *heathrow_pic_init(int nb_cpus, qemu_irq **irqs,

                               qemu_irq **pic_irqs)

{

    DeviceState *d;

    HeathrowState *s;



    d = qdev_create(NULL, TYPE_HEATHROW);

    qdev_init_nofail(d);



    s = HEATHROW(d);

    /* only 1 CPU */

    s->irqs = irqs[0];

    qdev_init_gpio_out(DEVICE(obj), s->irqs, 1);



    *pic_irqs = qemu_allocate_irqs(heathrow_set_irq, s, HEATHROW_NUM_IRQS);

    qdev_init_gpio_in(DEVICE(obj), heathrow_set_irq, HEATHROW_NUM_IRQS);



    return d;

    memory_region_init_io(&s->mem, OBJECT(s), &heathrow_ops, s,

                          "heathrow-pic", 0x1000);

    sysbus_init_mmio(sbd, &s->mem);

}



static void heathrow_class_init(ObjectClass *oc, void *data)

hw/misc/macio/macio.c

+22 −15
Original line number Diff line number Diff line
@@ -152,10 +152,9 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp) 
{

    MacIOState *s = MACIO(d);

    OldWorldMacIOState *os = OLDWORLD_MACIO(d);

    DeviceState *pic_dev = DEVICE(os->pic);

    Error *err = NULL;

    SysBusDevice *sysbus_dev;

    int i;

    int cur_irq = 0;



    macio_common_realize(d, &err);

    if (err) {
@@ -164,11 +163,14 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp) 
    }



    sysbus_dev = SYS_BUS_DEVICE(&s->cuda);

    sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]);

    sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,

                                                       OLDWORLD_CUDA_IRQ));



    sysbus_dev = SYS_BUS_DEVICE(&s->escc);

    sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]);

    sysbus_connect_irq(sysbus_dev, 1, os->irqs[cur_irq++]);

    sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,

                                                       OLDWORLD_ESCCB_IRQ));

    sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev,

                                                       OLDWORLD_ESCCA_IRQ));



    object_property_set_bool(OBJECT(&os->nvram), true, "realized", &err);

    if (err) {
@@ -186,15 +188,22 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp) 
                                sysbus_mmio_get_region(sysbus_dev, 0));



    /* IDE buses */

    for (i = 0; i < ARRAY_SIZE(os->ide); i++) {

        qemu_irq irq0 = os->irqs[cur_irq++];

        qemu_irq irq1 = os->irqs[cur_irq++];



        macio_realize_ide(s, &os->ide[i], irq0, irq1, 0x16 + (i * 4), &err);

    macio_realize_ide(s, &os->ide[0],

                      qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ),

                      qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_DMA_IRQ),

                      0x16, &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }



    macio_realize_ide(s, &os->ide[1],

                      qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_IRQ),

                      qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_DMA_IRQ),

                      0x1a, &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

}
@@ -219,8 +228,6 @@ static void macio_oldworld_init(Object *obj) 
    DeviceState *dev;

    int i;



    qdev_init_gpio_out(DEVICE(obj), os->irqs, ARRAY_SIZE(os->irqs));



    object_property_add_link(obj, "pic", TYPE_HEATHROW,

                             (Object **) &os->pic,

                             qdev_prop_allow_set_link_before_realize,