Commit dcaed66c authored by Peter Maydell's avatar Peter Maydell
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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.10-20170426' into staging 



ppc patch queue 2017-04-26

Here's a respind of my first pull request for qemu-2.10, consisting of
assorted patches which have accumulated while qemu-2.9 stabilized.
Highlights are:
    * Rework / cleanup of the XICS interrupt controller
    * Substantial improvement to the 'powernv' machine type
        - Includes an MMIO XICS version
    * POWER9 support improvements
        - POWER9 guests with KVM
        - Partial support for POWER9 guests with TCG
    * IOMMU and VFIO improvements
    * Assorted minor changes

There are several IPMI patches here that aren't usually in my area of
maintenance, but there isn't a regular maintainer and these patches
are for the benefit of the powernv machine type.

This pull request supersedes my 2017-04-26 pull request.  This new set
fixes a bug in one of the aforementioned IPMI patches which caused
clang sanitizer failures (and may have crashed on some libc / host
versions).

# gpg: Signature made Wed 26 Apr 2017 07:58:10 BST
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>"
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>"
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.10-20170426: (48 commits)
  MAINTAINERS: Remove myself from e500
  target/ppc: Style fixes
  e500,book3s: mfspr 259: Register mapped/aliased SPRG3 user read
  target/ppc: Flush TLB on write to PIDR
  spapr-cpu-core: Release ICPState object during CPU unrealization
  ppc/pnv: generate an OEM SEL event on shutdown
  ppc/pnv: add initial IPMI sensors for the BMC simulator
  ppc/pnv: populate device tree for IPMI BT devices
  ppc/pnv: populate device tree for serial devices
  ppc/pnv: populate device tree for RTC devices
  ppc/pnv: scan ISA bus to populate device tree
  ppc/pnv: enable only one LPC bus
  ppc/pnv: Add support for POWER8+ LPC Controller
  spapr: remove the 'nr_servers' field from the machine
  target/ppc: Fix size of struct PPCElfPrstatus
  ipmi: introduce an ipmi_bmc_gen_event() API
  ipmi: introduce an ipmi_bmc_sdr_find() API
  ipmi: provide support for FRUs
  ipmi: use a file to load SDRs
  ppc: add IPMI support
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 52e94ea5 df02d2ca

MAINTAINERS

+0 −3
Original line number Diff line number Diff line
@@ -646,7 +646,6 @@ F: hw/ppc/ppc440_bamboo.c 


e500

M: Alexander Graf <agraf@suse.de>

M: Scott Wood <scottwood@freescale.com>

L: qemu-ppc@nongnu.org

S: Supported

F: hw/ppc/e500.[hc]
@@ -657,7 +656,6 @@ F: pc-bios/u-boot.e500 


mpc8544ds

M: Alexander Graf <agraf@suse.de>

M: Scott Wood <scottwood@freescale.com>

L: qemu-ppc@nongnu.org

S: Supported

F: hw/ppc/mpc8544ds.c
@@ -934,7 +932,6 @@ F: include/hw/ppc/ppc4xx.h 


ppce500

M: Alexander Graf <agraf@suse.de>

M: Scott Wood <scottwood@freescale.com>

L: qemu-ppc@nongnu.org

S: Supported

F: hw/ppc/e500*

default-configs/ppc64-softmmu.mak

+4 −0
Original line number Diff line number Diff line
@@ -6,6 +6,10 @@ include usb.mak 
CONFIG_VIRTIO_VGA=y

CONFIG_ESCC=y

CONFIG_M48T59=y

CONFIG_IPMI=y

CONFIG_IPMI_LOCAL=y

CONFIG_IPMI_EXTERN=y

CONFIG_ISA_IPMI_BT=y

CONFIG_SERIAL=y

CONFIG_PARALLEL=y

CONFIG_I8254=y

hw/intc/Makefile.objs

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ obj-$(CONFIG_SH4) += sh_intc.o 
obj-$(CONFIG_XICS) += xics.o

obj-$(CONFIG_XICS_SPAPR) += xics_spapr.o

obj-$(CONFIG_XICS_KVM) += xics_kvm.o

obj-$(CONFIG_POWERNV) += xics_pnv.o

obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o

obj-$(CONFIG_S390_FLIC) += s390_flic.o

obj-$(CONFIG_S390_FLIC_KVM) += s390_flic_kvm.o

hw/intc/xics.c

+8 −14
Original line number Diff line number Diff line
@@ -38,21 +38,10 @@ 
#include "monitor/monitor.h"

#include "hw/intc/intc.h"



int xics_get_cpu_index_by_dt_id(int cpu_dt_id)

{

    PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);



    if (cpu) {

        return cpu->parent_obj.cpu_index;

    }



    return -1;

}



void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu)

{

    CPUState *cs = CPU(cpu);

    ICPState *icp = xics_icp_get(xi, cs->cpu_index);

    ICPState *icp = ICP(cpu->intc);



    assert(icp);

    assert(cs == icp->cs);
@@ -61,15 +50,15 @@ void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu) 
    icp->cs = NULL;

}



void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu)

void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu, ICPState *icp)

{

    CPUState *cs = CPU(cpu);

    CPUPPCState *env = &cpu->env;

    ICPState *icp = xics_icp_get(xi, cs->cpu_index);

    ICPStateClass *icpc;



    assert(icp);



    cpu->intc = OBJECT(icp);

    icp->cs = cs;



    icpc = ICP_GET_CLASS(icp);
@@ -348,6 +337,7 @@ static void icp_reset(void *dev) 
static void icp_realize(DeviceState *dev, Error **errp)

{

    ICPState *icp = ICP(dev);

    ICPStateClass *icpc = ICP_GET_CLASS(dev);

    Object *obj;

    Error *err = NULL;
@@ -360,6 +350,10 @@ static void icp_realize(DeviceState *dev, Error **errp) 


    icp->xics = XICS_FABRIC(obj);



    if (icpc->realize) {

        icpc->realize(dev, errp);

    }



    qemu_register_reset(icp_reset, dev);

}

hw/intc/xics_pnv.c

0 → 100644
+192 −0
Original line number Diff line number Diff line 
/*

 * QEMU PowerPC PowerNV Interrupt Control Presenter (ICP) model

 *

 * Copyright (c) 2017, IBM Corporation.

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public License

 * as published by the Free Software Foundation; either version 2 of

 * the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful, but

 * WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, see <http://www.gnu.org/licenses/>.

 */



#include "qemu/osdep.h"

#include "sysemu/sysemu.h"

#include "qapi/error.h"

#include "qemu/log.h"

#include "hw/ppc/xics.h"



#define ICP_XIRR_POLL    0 /* 1 byte (CPRR) or 4 bytes */

#define ICP_XIRR         4 /* 1 byte (CPRR) or 4 bytes */

#define ICP_MFRR        12 /* 1 byte access only */



#define ICP_LINKA       16 /* unused */

#define ICP_LINKB       20 /* unused */

#define ICP_LINKC       24 /* unused */



static uint64_t pnv_icp_read(void *opaque, hwaddr addr, unsigned width)

{

    ICPState *icp = ICP(opaque);

    PnvICPState *picp = PNV_ICP(opaque);

    bool byte0 = (width == 1 && (addr & 0x3) == 0);

    uint64_t val = 0xffffffff;



    switch (addr & 0xffc) {

    case ICP_XIRR_POLL:

        val = icp_ipoll(icp, NULL);

        if (byte0) {

            val >>= 24;

        } else if (width != 4) {

            goto bad_access;

        }

        break;

    case ICP_XIRR:

        if (byte0) {

            val = icp_ipoll(icp, NULL) >> 24;

        } else if (width == 4) {

            val = icp_accept(icp);

        } else {

            goto bad_access;

        }

        break;

    case ICP_MFRR:

        if (byte0) {

            val = icp->mfrr;

        } else {

            goto bad_access;

        }

        break;

    case ICP_LINKA:

        if (width == 4) {

            val = picp->links[0];

        } else {

            goto bad_access;

        }

        break;

    case ICP_LINKB:

        if (width == 4) {

            val = picp->links[1];

        } else {

            goto bad_access;

        }

        break;

    case ICP_LINKC:

        if (width == 4) {

            val = picp->links[2];

        } else {

            goto bad_access;

        }

        break;

    default:

bad_access:

        qemu_log_mask(LOG_GUEST_ERROR, "XICS: Bad ICP access 0x%"

                      HWADDR_PRIx"/%d\n", addr, width);

    }



    return val;

}



static void pnv_icp_write(void *opaque, hwaddr addr, uint64_t val,

                              unsigned width)

{

    ICPState *icp = ICP(opaque);

    PnvICPState *picp = PNV_ICP(opaque);

    bool byte0 = (width == 1 && (addr & 0x3) == 0);



    switch (addr & 0xffc) {

    case ICP_XIRR:

        if (byte0) {

            icp_set_cppr(icp, val);

        } else if (width == 4) {

            icp_eoi(icp, val);

        } else {

            goto bad_access;

        }

        break;

    case ICP_MFRR:

        if (byte0) {

            icp_set_mfrr(icp, val);

        } else {

            goto bad_access;

        }

        break;

    case ICP_LINKA:

        if (width == 4) {

            picp->links[0] = val;

        } else {

            goto bad_access;

        }

        break;

    case ICP_LINKB:

        if (width == 4) {

            picp->links[1] = val;

        } else {

            goto bad_access;

        }

        break;

    case ICP_LINKC:

        if (width == 4) {

            picp->links[2] = val;

        } else {

            goto bad_access;

        }

        break;

    default:

bad_access:

        qemu_log_mask(LOG_GUEST_ERROR, "XICS: Bad ICP access 0x%"

                      HWADDR_PRIx"/%d\n", addr, width);

    }

}



static const MemoryRegionOps pnv_icp_ops = {

    .read = pnv_icp_read,

    .write = pnv_icp_write,

    .endianness = DEVICE_BIG_ENDIAN,

    .valid = {

        .min_access_size = 1,

        .max_access_size = 4,

    },

    .impl = {

        .min_access_size = 1,

        .max_access_size = 4,

    },

};



static void pnv_icp_realize(DeviceState *dev, Error **errp)

{

    PnvICPState *icp = PNV_ICP(dev);



    memory_region_init_io(&icp->mmio, OBJECT(dev), &pnv_icp_ops,

                          icp, "icp-thread", 0x1000);

}



static void pnv_icp_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);

    ICPStateClass *icpc = ICP_CLASS(klass);



    icpc->realize = pnv_icp_realize;

    dc->desc = "PowerNV ICP";

}



static const TypeInfo pnv_icp_info = {

    .name          = TYPE_PNV_ICP,

    .parent        = TYPE_ICP,

    .instance_size = sizeof(PnvICPState),

    .class_init    = pnv_icp_class_init,

    .class_size    = sizeof(ICPStateClass),

};



static void pnv_icp_register_types(void)

{

    type_register_static(&pnv_icp_info);

}



type_init(pnv_icp_register_types)