Commit dc65a5bd authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200108' into staging 



ppc patch queue 2020-01-08

Here's another pull request for qemu-5.0 of ppc related changes.
Highlights are:
 * First parts of support for POWER Secure VMs
 * Rework to clean up how we pass context information to the various
   components of the pnv machine (reduces usage of qdev_get_machine())
 * Assorted cleanups and bugfixes

# gpg: Signature made Wed 08 Jan 2020 05:22:08 GMT
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-5.0-20200108: (26 commits)
  ppc/pnv: fix check on return value of blk_getlength()
  ppc/pnv: check return value of blk_pwrite()
  pnv/psi: Consolidate some duplicated code in pnv_psi_realize()
  pnv/psi: Add device reset hook
  pnv/xive: Deduce the PnvXive pointer from XiveTCTX::xptr
  spapr/xive: Deduce the SpaprXive pointer from XiveTCTX::xptr
  xive: Add a "presenter" link property to the TCTX object
  ppc/pnv: Add a "pnor" const link property to the BMC internal simulator
  ppc/pnv: Add an "nr-threads" property to the base chip class
  xive: Use the XIVE fabric link under the XIVE router
  spapr, pnv, xive: Add a "xive-fabric" link to the XIVE router
  pnv/xive: Use device_class_set_parent_realize()
  ppc/pnv: Introduce a "xics" property under the POWER8 chip
  ppc/pnv: Introduce a "xics" property alias under the PSI model
  spapr/xive: remove redundant check in spapr_match_nvt()
  ppc/pnv: Drop "num-chips" machine property
  ppc440_bamboo.c: remove label from bamboo_load_device_tree()
  spapr.c: remove 'out' label in spapr_dt_cas_updates()
  ppc/spapr: Don't call KVM_SVM_OFF ioctl on TCG
  spapr/xive: Use device_class_set_parent_realize()
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents f38a71b0 fc2527fb

hw/intc/pnv_xive.c

+12 −6
Original line number Diff line number Diff line
@@ -472,12 +472,8 @@ static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr) 
static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)

{

    int pir = ppc_cpu_pir(cpu);

    PnvChip *chip;

    PnvXive *xive;



    chip = pnv_get_chip(PNV9_PIR2CHIP(pir));

    assert(chip);

    xive = &PNV9_CHIP(chip)->xive;

    XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr;

    PnvXive *xive = PNV_XIVE(xptr);



    if (!pnv_xive_is_cpu_enabled(xive, cpu)) {

        xive_error(xive, "IC: CPU %x is not enabled", pir);
@@ -1816,10 +1812,17 @@ static void pnv_xive_init(Object *obj) 
static void pnv_xive_realize(DeviceState *dev, Error **errp)

{

    PnvXive *xive = PNV_XIVE(dev);

    PnvXiveClass *pxc = PNV_XIVE_GET_CLASS(dev);

    XiveSource *xsrc = &xive->ipi_source;

    XiveENDSource *end_xsrc = &xive->end_source;

    Error *local_err = NULL;



    pxc->parent_realize(dev, &local_err);

    if (local_err) {

        error_propagate(errp, local_err);

        return;

    }



    assert(xive->chip);



    /*
@@ -1947,10 +1950,12 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data) 
    XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass);

    XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);

    XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass);

    PnvXiveClass *pxc = PNV_XIVE_CLASS(klass);



    xdc->dt_xscom = pnv_xive_dt_xscom;



    dc->desc = "PowerNV XIVE Interrupt Controller";

    device_class_set_parent_realize(dc, pnv_xive_realize, &pxc->parent_realize);

    dc->realize = pnv_xive_realize;

    dc->props = pnv_xive_properties;
@@ -1971,6 +1976,7 @@ static const TypeInfo pnv_xive_info = { 
    .instance_init = pnv_xive_init,

    .instance_size = sizeof(PnvXive),

    .class_init    = pnv_xive_class_init,

    .class_size    = sizeof(PnvXiveClass),

    .interfaces    = (InterfaceInfo[]) {

        { TYPE_PNV_XSCOM_INTERFACE },

        { }

hw/intc/spapr_xive.c

+12 −2
Original line number Diff line number Diff line
@@ -286,10 +286,17 @@ static void spapr_xive_instance_init(Object *obj) 
static void spapr_xive_realize(DeviceState *dev, Error **errp)

{

    SpaprXive *xive = SPAPR_XIVE(dev);

    SpaprXiveClass *sxc = SPAPR_XIVE_GET_CLASS(xive);

    XiveSource *xsrc = &xive->source;

    XiveENDSource *end_xsrc = &xive->end_source;

    Error *local_err = NULL;



    sxc->parent_realize(dev, &local_err);

    if (local_err) {

        error_propagate(errp, local_err);

        return;

    }



    if (!xive->nr_irqs) {

        error_setg(errp, "Number of interrupt needs to be greater 0");

        return;
@@ -594,7 +601,7 @@ static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 
    Object *obj;

    SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);



    obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp);

    obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(xive), errp);

    if (!obj) {

        return -1;

    }
@@ -760,10 +767,12 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data) 
    XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass);

    SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass);

    XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass);

    SpaprXiveClass *sxc = SPAPR_XIVE_CLASS(klass);



    dc->desc    = "sPAPR XIVE Interrupt Controller";

    dc->props   = spapr_xive_properties;

    dc->realize = spapr_xive_realize;

    device_class_set_parent_realize(dc, spapr_xive_realize,

                                    &sxc->parent_realize);

    dc->vmsd    = &vmstate_spapr_xive;



    xrc->get_eas = spapr_xive_get_eas;
@@ -794,6 +803,7 @@ static const TypeInfo spapr_xive_info = { 
    .instance_init = spapr_xive_instance_init,

    .instance_size = sizeof(SpaprXive),

    .class_init = spapr_xive_class_init,

    .class_size = sizeof(SpaprXiveClass),

    .interfaces = (InterfaceInfo[]) {

        { TYPE_SPAPR_INTC },

        { }

hw/intc/spapr_xive_kvm.c

+4 −5
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ static void kvm_cpu_disable_all(void) 


void kvmppc_xive_cpu_set_state(XiveTCTX *tctx, Error **errp)

{

    SpaprXive *xive = SPAPR_MACHINE(qdev_get_machine())->xive;

    SpaprXive *xive = SPAPR_XIVE(tctx->xptr);

    uint64_t state[2];

    int ret;
@@ -97,7 +97,7 @@ void kvmppc_xive_cpu_set_state(XiveTCTX *tctx, Error **errp) 


void kvmppc_xive_cpu_get_state(XiveTCTX *tctx, Error **errp)

{

    SpaprXive *xive = SPAPR_MACHINE(qdev_get_machine())->xive;

    SpaprXive *xive = SPAPR_XIVE(tctx->xptr);

    uint64_t state[2] = { 0 };

    int ret;
@@ -152,8 +152,7 @@ void kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx, Error **errp) 


void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp)

{

    MachineState *ms = MACHINE(qdev_get_machine());

    SpaprXive *xive = SPAPR_MACHINE(ms)->xive;

    SpaprXive *xive = SPAPR_XIVE(tctx->xptr);

    unsigned long vcpu_id;

    int ret;
@@ -179,7 +178,7 @@ void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp) 
                   vcpu_id, strerror(errno));

        if (errno == ENOSPC) {

            error_append_hint(&local_err, "Try -smp maxcpus=N with N < %u\n",

                              ms->smp.max_cpus);

                              MACHINE(qdev_get_machine())->smp.max_cpus);

        }

        error_propagate(errp, local_err);

        return;

hw/intc/xive.c

+24 −4
Original line number Diff line number Diff line
@@ -654,6 +654,7 @@ static void xive_tctx_realize(DeviceState *dev, Error **errp) 
    Error *local_err = NULL;



    assert(tctx->cs);

    assert(tctx->xptr);



    cpu = POWERPC_CPU(tctx->cs);

    env = &cpu->env;
@@ -727,6 +728,8 @@ static const VMStateDescription vmstate_xive_tctx = { 


static Property xive_tctx_properties[] = {

    DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *),

    DEFINE_PROP_LINK("presenter", XiveTCTX, xptr, TYPE_XIVE_PRESENTER,

                     XivePresenter *),

    DEFINE_PROP_END_OF_LIST(),

};
@@ -752,7 +755,7 @@ static const TypeInfo xive_tctx_info = { 
    .class_init    = xive_tctx_class_init,

};



Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp)

Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp)

{

    Error *local_err = NULL;

    Object *obj;
@@ -761,6 +764,7 @@ Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) 
    object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort);

    object_unref(obj);

    object_property_set_link(obj, cpu, "cpu", &error_abort);

    object_property_set_link(obj, OBJECT(xptr), "presenter", &error_abort);

    object_property_set_bool(obj, true, "realized", &local_err);

    if (local_err) {

        goto error;
@@ -1378,6 +1382,13 @@ static int xive_router_get_block_id(XiveRouter *xrtr) 
   return xrc->get_block_id(xrtr);

}



static void xive_router_realize(DeviceState *dev, Error **errp)

{

    XiveRouter *xrtr = XIVE_ROUTER(dev);



    assert(xrtr->xfb);

}



/*

 * Encode the HW CAM line in the block group mode format :

 *
@@ -1470,12 +1481,11 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 
 *

 * The parameters represent what is sent on the PowerBus

 */

static bool xive_presenter_notify(uint8_t format,

static bool xive_presenter_notify(XiveFabric *xfb, uint8_t format,

                                  uint8_t nvt_blk, uint32_t nvt_idx,

                                  bool cam_ignore, uint8_t priority,

                                  uint32_t logic_serv)

{

    XiveFabric *xfb = XIVE_FABRIC(qdev_get_machine());

    XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb);

    XiveTCTXMatch match = { .tctx = NULL, .ring = 0 };

    int count;
@@ -1607,7 +1617,7 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, 
        return;

    }



    found = xive_presenter_notify(format, nvt_blk, nvt_idx,

    found = xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx,

                          xive_get_field32(END_W7_F0_IGNORE, end.w7),

                          priority,

                          xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7));
@@ -1714,12 +1724,21 @@ void xive_router_notify(XiveNotifier *xn, uint32_t lisn) 
                           xive_get_field64(EAS_END_DATA,  eas.w));

}



static Property xive_router_properties[] = {

    DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb,

                     TYPE_XIVE_FABRIC, XiveFabric *),

    DEFINE_PROP_END_OF_LIST(),

};



static void xive_router_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);

    XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);



    dc->desc    = "XIVE Router Engine";

    dc->props   = xive_router_properties;

    /* Parent is SysBusDeviceClass. No need to call its realize hook */

    dc->realize = xive_router_realize;

    xnc->notify = xive_router_notify;

}
@@ -1727,6 +1746,7 @@ static const TypeInfo xive_router_info = { 
    .name          = TYPE_XIVE_ROUTER,

    .parent        = TYPE_SYS_BUS_DEVICE,

    .abstract      = true,

    .instance_size = sizeof(XiveRouter),

    .class_size    = sizeof(XiveRouterClass),

    .class_init    = xive_router_class_init,

    .interfaces    = (InterfaceInfo[]) {

hw/misc/mos6522.c

+8 −8
Original line number Diff line number Diff line
@@ -244,6 +244,9 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) 
        val = s->b;

        break;

    case VIA_REG_A:

       qemu_log_mask(LOG_UNIMP, "Read access to register A with handshake");

       /* fall through */

    case VIA_REG_ANH:

        val = s->a;

        break;

    case VIA_REG_DIRB:
@@ -297,9 +300,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) 
        val = s->ier | 0x80;

        break;

    default:

    case VIA_REG_ANH:

        val = s->anh;

        break;

        g_assert_not_reached();

    }



    if (addr != VIA_REG_IFR || val != 0) {
@@ -322,6 +323,9 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) 
        mdc->portB_write(s);

        break;

    case VIA_REG_A:

       qemu_log_mask(LOG_UNIMP, "Write access to register A with handshake");

       /* fall through */

    case VIA_REG_ANH:

        s->a = (s->a & ~s->dira) | (val & s->dira);

        mdc->portA_write(s);

        break;
@@ -395,9 +399,7 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) 
                              qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));

        break;

    default:

    case VIA_REG_ANH:

        s->anh = val;

        break;

        g_assert_not_reached();

    }

}
@@ -439,7 +441,6 @@ const VMStateDescription vmstate_mos6522 = { 
        VMSTATE_UINT8(pcr, MOS6522State),

        VMSTATE_UINT8(ifr, MOS6522State),

        VMSTATE_UINT8(ier, MOS6522State),

        VMSTATE_UINT8(anh, MOS6522State),

        VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 0,

                             vmstate_mos6522_timer, MOS6522Timer),

        VMSTATE_END_OF_LIST()
@@ -460,7 +461,6 @@ static void mos6522_reset(DeviceState *dev) 
    s->ifr = 0;

    s->ier = 0;

    /* s->ier = T1_INT | SR_INT; */

    s->anh = 0;



    s->timers[0].frequency = s->frequency;

    s->timers[0].latch = 0xffff;