Commit dba519a2 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/kraxel/tags/vga-20190705-pull-request' into staging 



vga: more ati bugfixes.

# gpg: Signature made Fri 05 Jul 2019 14:42:30 BST
# gpg:                using RSA key 4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138

* remotes/kraxel/tags/vga-20190705-pull-request:
  ati-vga: Fix setting offset together with pitch for r128pro
  ati-vga: Fix reverse bit blts
  ati-vga: Fix frame buffer endianness for big endian target
  ati-vga: Improve readability of ati_2d_blt function

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 0050f997 146dd326

hw/display/ati.c

+3 −2
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ static void ati_vga_switch_mode(ATIVGAState *s) 
            DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, offs);

            vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);

            vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED);

            s->vga.big_endian_fb = false;

            /* reset VBE regs then set up mode */

            s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] = h;

            s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] = v;
@@ -688,7 +689,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, 
        break;

    case SRC_PITCH_OFFSET:

        if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {

            s->regs.src_offset = (data & 0x1fffff) << 4;

            s->regs.src_offset = (data & 0x1fffff) << 5;

            s->regs.src_pitch = (data & 0x7fe00000) >> 21;

            s->regs.src_tile = data >> 31;

        } else {
@@ -699,7 +700,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, 
        break;

    case DST_PITCH_OFFSET:

        if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {

            s->regs.dst_offset = (data & 0x1fffff) << 4;

            s->regs.dst_offset = (data & 0x1fffff) << 5;

            s->regs.dst_pitch = (data & 0x7fe00000) >> 21;

            s->regs.dst_tile = data >> 31;

        } else {

hw/display/ati_2d.c

+72 −61
Original line number Diff line number Diff line
@@ -42,6 +42,8 @@ static int ati_bpp_from_datatype(ATIVGAState *s) 
    }

}



#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL)



void ati_2d_blt(ATIVGAState *s)

{

    /* FIXME it is probably more complex than this and may need to be */
@@ -51,60 +53,88 @@ void ati_2d_blt(ATIVGAState *s) 
            s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds),

            surface_bits_per_pixel(ds),

            (s->regs.dp_mix & GMC_ROP3_MASK) >> 16);

    DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d\n",

    int dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?

                 s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width);

    int dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?

                 s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height);

    int bpp = ati_bpp_from_datatype(s);

    int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch;

    uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?

                        s->regs.dst_offset : s->regs.default_offset);



    if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {

        dst_bits += s->regs.crtc_offset & 0x07ffffff;

        dst_stride *= bpp;

    }

    uint8_t *end = s->vga.vram_ptr + s->vga.vram_size;

    if (dst_bits >= end || dst_bits + dst_x + (dst_y + s->regs.dst_height) *

        dst_stride >= end) {

        qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");

        return;

    }

    DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n",

            s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset,

            s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch,

            s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,

            s->regs.dst_width, s->regs.dst_height);

            s->regs.dst_width, s->regs.dst_height,

            (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'),

            (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^'));

    switch (s->regs.dp_mix & GMC_ROP3_MASK) {

    case ROP3_SRCCOPY:

    {

        uint8_t *src_bits, *dst_bits, *end;

        int src_stride, dst_stride, bpp = ati_bpp_from_datatype(s);

        src_bits = s->vga.vram_ptr +

                   (s->regs.dp_gui_master_cntl & GMC_SRC_PITCH_OFFSET_CNTL ?

        int src_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?

                     s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width);

        int src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?

                     s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height);

        int src_stride = DEFAULT_CNTL ?

                         s->regs.src_pitch : s->regs.default_pitch;

        uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?

                            s->regs.src_offset : s->regs.default_offset);

        dst_bits = s->vga.vram_ptr +

                   (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ?

                    s->regs.dst_offset : s->regs.default_offset);

        src_stride = (s->regs.dp_gui_master_cntl & GMC_SRC_PITCH_OFFSET_CNTL ?

                      s->regs.src_pitch : s->regs.default_pitch);

        dst_stride = (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ?

                      s->regs.dst_pitch : s->regs.default_pitch);



        if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {

            src_bits += s->regs.crtc_offset & 0x07ffffff;

            dst_bits += s->regs.crtc_offset & 0x07ffffff;

            src_stride *= bpp;

            dst_stride *= bpp;

        }

        if (src_bits >= end || src_bits + src_x +

            (src_y + s->regs.dst_height) * src_stride >= end) {

            qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");

            return;

        }



        src_stride /= sizeof(uint32_t);

        dst_stride /= sizeof(uint32_t);



        DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n",

                src_bits, dst_bits, src_stride, dst_stride, bpp, bpp,

                s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,

                src_x, src_y, dst_x, dst_y,

                s->regs.dst_width, s->regs.dst_height);

        end = s->vga.vram_ptr + s->vga.vram_size;

        if (src_bits >= end || dst_bits >= end ||

            src_bits + s->regs.src_x + (s->regs.src_y + s->regs.dst_height) *

            src_stride * sizeof(uint32_t) >= end ||

            dst_bits + s->regs.dst_x + (s->regs.dst_y + s->regs.dst_height) *

            dst_stride * sizeof(uint32_t) >= end) {

            qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");

            return;

        }

        if (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT &&

            s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) {

            pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits,

                       src_stride, dst_stride, bpp, bpp,

                   s->regs.src_x, s->regs.src_y,

                   s->regs.dst_x, s->regs.dst_y,

                       src_x, src_y, dst_x, dst_y,

                       s->regs.dst_width, s->regs.dst_height);

        } else {

            /* FIXME: We only really need a temporary if src and dst overlap */

            int llb = s->regs.dst_width * (bpp / 8);

            int tmp_stride = DIV_ROUND_UP(llb, sizeof(uint32_t));

            uint32_t *tmp = g_malloc(tmp_stride * sizeof(uint32_t) *

                                     s->regs.dst_height);

            pixman_blt((uint32_t *)src_bits, tmp,

                       src_stride, tmp_stride, bpp, bpp,

                       src_x, src_y, 0, 0,

                       s->regs.dst_width, s->regs.dst_height);

            pixman_blt(tmp, (uint32_t *)dst_bits,

                       tmp_stride, dst_stride, bpp, bpp,

                       0, 0, dst_x, dst_y,

                       s->regs.dst_width, s->regs.dst_height);

            g_free(tmp);

        }

        if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&

            dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +

            s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {

            memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +

                                    s->regs.dst_offset +

                                    s->regs.dst_y * surface_stride(ds),

                                    dst_y * surface_stride(ds),

                                    s->regs.dst_height * surface_stride(ds));

        }

        s->regs.dst_x += s->regs.dst_width;
@@ -115,47 +145,28 @@ void ati_2d_blt(ATIVGAState *s) 
    case ROP3_BLACKNESS:

    case ROP3_WHITENESS:

    {

        uint8_t *dst_bits, *end;

        int dst_stride, bpp = ati_bpp_from_datatype(s);

        uint32_t filler = 0;

        dst_bits = s->vga.vram_ptr +

                   (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ?

                    s->regs.dst_offset : s->regs.default_offset);

        dst_stride = (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ?

                      s->regs.dst_pitch : s->regs.default_pitch);



        if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {

            dst_bits += s->regs.crtc_offset & 0x07ffffff;

            dst_stride *= bpp;

        }

        dst_stride /= sizeof(uint32_t);



        switch (s->regs.dp_mix & GMC_ROP3_MASK) {

        case ROP3_PATCOPY:

            filler = bswap32(s->regs.dp_brush_frgd_clr);

            filler = s->regs.dp_brush_frgd_clr;

            break;

        case ROP3_BLACKNESS:

            filler = rgb_to_pixel32(s->vga.palette[0], s->vga.palette[1],

                                    s->vga.palette[2]) << 8 | 0xff;

            filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[0],

                     s->vga.palette[1], s->vga.palette[2]);

            break;

        case ROP3_WHITENESS:

            filler = rgb_to_pixel32(s->vga.palette[3], s->vga.palette[4],

                                    s->vga.palette[5]) << 8 | 0xff;

            filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[3],

                     s->vga.palette[4], s->vga.palette[5]);

            break;

        }



        dst_stride /= sizeof(uint32_t);

        DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n",

                dst_bits, dst_stride, bpp,

                s->regs.dst_x, s->regs.dst_y,

                s->regs.dst_width, s->regs.dst_height,

                filler);

        end = s->vga.vram_ptr + s->vga.vram_size;

        if (dst_bits >= end ||

            dst_bits + s->regs.dst_x + (s->regs.dst_y + s->regs.dst_height) *

            dst_stride * sizeof(uint32_t) >= end) {

            qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");

            return;

        }

        pixman_fill((uint32_t *)dst_bits, dst_stride, bpp,

                    s->regs.dst_x, s->regs.dst_y,

                    s->regs.dst_width, s->regs.dst_height,
@@ -165,7 +176,7 @@ void ati_2d_blt(ATIVGAState *s) 
            s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {

            memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +

                                    s->regs.dst_offset +

                                    s->regs.dst_y * surface_stride(ds),

                                    dst_y * surface_stride(ds),

                                    s->regs.dst_height * surface_stride(ds));

        }

        s->regs.dst_y += s->regs.dst_height;