Commit da378d01 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150427' into staging 



target-arm queue:
 * memory system updates to support transaction attributes
 * set user-mode and secure attributes for accesses made by ARM CPUs
 * rename c1_coproc to cpacr_el1
 * adjust id_aa64pfr0 when has_el3 CPU property disabled
 * allow ARMv8 SCR.SMD updates

# gpg: Signature made Mon Apr 27 16:14:30 2015 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20150427:
  Allow ARMv8 SCR.SMD updates
  target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled
  target-arm: rename c1_coproc to cpacr_el1
  target-arm: Check watchpoints against CPU security state
  target-arm: Use attribute info to handle user-only watchpoints
  target-arm: Add user-mode transaction attribute
  target-arm: Use correct memory attributes for page table walks
  target-arm: Honour NS bits in page tables
  Switch non-CPU callers from ld/st*_phys to address_space_ld/st*
  exec.c: Capture the memory attributes for a watchpoint hit
  exec.c: Add new address_space_ld*/st* functions
  exec.c: Make address_space_rw take transaction attributes
  exec.c: Convert subpage memory ops to _with_attrs
  Add MemTxAttrs to the IOTLB
  Make CPU iotlb a structure rather than a plain hwaddr
  memory: Replace io_mem_read/write with memory_region_dispatch_read/write
  memory: Define API for MemoryRegionOps to take attrs and return status

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 3d27b09c 4eb27640

cputlb.c

+17 −5
Original line number Diff line number Diff line
@@ -249,8 +249,8 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr, 
 * Called from TCG-generated code, which is under an RCU read-side

 * critical section.

 */

void tlb_set_page(CPUState *cpu, target_ulong vaddr,

                  hwaddr paddr, int prot,

void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,

                             hwaddr paddr, MemTxAttrs attrs, int prot,

                             int mmu_idx, target_ulong size)

{

    CPUArchState *env = cpu->env_ptr;
@@ -301,7 +301,8 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, 
    env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];



    /* refill the tlb */

    env->iotlb[mmu_idx][index] = iotlb - vaddr;

    env->iotlb[mmu_idx][index].addr = iotlb - vaddr;

    env->iotlb[mmu_idx][index].attrs = attrs;

    te->addend = addend - vaddr;

    if (prot & PAGE_READ) {

        te->addr_read = address;
@@ -331,6 +332,17 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, 
    }

}



/* Add a new TLB entry, but without specifying the memory

 * transaction attributes to be used.

 */

void tlb_set_page(CPUState *cpu, target_ulong vaddr,

                  hwaddr paddr, int prot,

                  int mmu_idx, target_ulong size)

{

    tlb_set_page_with_attrs(cpu, vaddr, paddr, MEMTXATTRS_UNSPECIFIED,

                            prot, mmu_idx, size);

}



/* NOTE: this function can trigger an exception */

/* NOTE2: the returned address is not exactly the physical address: it

 * is actually a ram_addr_t (in system mode; the user mode emulation
@@ -349,7 +361,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) 
                 (addr & TARGET_PAGE_MASK))) {

        cpu_ldub_code(env1, addr);

    }

    pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;

    pd = env1->iotlb[mmu_idx][page_index].addr & ~TARGET_PAGE_MASK;

    mr = iotlb_to_region(cpu, pd);

    if (memory_region_is_unassigned(mr)) {

        CPUClass *cc = CPU_GET_CLASS(cpu);

dma-helpers.c

+2 −1
Original line number Diff line number Diff line
@@ -28,7 +28,8 @@ int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len) 
    memset(fillbuf, c, FILLBUF_SIZE);

    while (len > 0) {

        l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE;

        error |= address_space_rw(as, addr, fillbuf, l, true);

        error |= address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED,

                                  fillbuf, l, true);

        len -= l;

        addr += l;

    }

exec.c

+334 −92

File changed.

Preview size limit exceeded, changes collapsed.

hw/alpha/dp264.c

+6 −3
Original line number Diff line number Diff line
@@ -157,9 +157,12 @@ static void clipper_init(MachineState *machine) 
            load_image_targphys(initrd_filename, initrd_base,

                                ram_size - initrd_base);



            stq_phys(&address_space_memory,

                     param_offset + 0x100, initrd_base + 0xfffffc0000000000ULL);

            stq_phys(&address_space_memory, param_offset + 0x108, initrd_size);

            address_space_stq(&address_space_memory, param_offset + 0x100,

                              initrd_base + 0xfffffc0000000000ULL,

                              MEMTXATTRS_UNSPECIFIED,

                              NULL);

            address_space_stq(&address_space_memory, param_offset + 0x108,

                              initrd_size, MEMTXATTRS_UNSPECIFIED, NULL);

        }

    }

}

hw/alpha/typhoon.c

+2 −1
Original line number Diff line number Diff line
@@ -613,7 +613,8 @@ static bool make_iommu_tlbe(hwaddr taddr, hwaddr mask, IOMMUTLBEntry *ret) 
   translation, given the address of the PTE.  */

static bool pte_translate(hwaddr pte_addr, IOMMUTLBEntry *ret)

{

    uint64_t pte = ldq_phys(&address_space_memory, pte_addr);

    uint64_t pte = address_space_ldq(&address_space_memory, pte_addr,

                                     MEMTXATTRS_UNSPECIFIED, NULL);



    /* Check valid bit.  */

    if ((pte & 1) == 0) {