Commit d9f482a0 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Add new_pc argument to helper_exception_return 



Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190108223129.5570-12-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent ce02fd99

target/arm/helper-a64.c

+5 −5
Original line number Diff line number Diff line
@@ -925,7 +925,7 @@ static int el_from_spsr(uint32_t spsr) 
    }

}



void HELPER(exception_return)(CPUARMState *env)

void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)

{

    int cur_el = arm_current_el(env);

    unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
@@ -991,9 +991,9 @@ void HELPER(exception_return)(CPUARMState *env) 
        aarch64_sync_64_to_32(env);



        if (spsr & CPSR_T) {

            env->regs[15] = env->elr_el[cur_el] & ~0x1;

            env->regs[15] = new_pc & ~0x1;

        } else {

            env->regs[15] = env->elr_el[cur_el] & ~0x3;

            env->regs[15] = new_pc & ~0x3;

        }

        qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "

                      "AArch32 EL%d PC 0x%" PRIx32 "\n",
@@ -1005,7 +1005,7 @@ void HELPER(exception_return)(CPUARMState *env) 
            env->pstate &= ~PSTATE_SS;

        }

        aarch64_restore_sp(env, new_el);

        env->pc = env->elr_el[cur_el];

        env->pc = new_pc;

        qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "

                      "AArch64 EL%d PC 0x%" PRIx64 "\n",

                      cur_el, new_el, env->pc);
@@ -1031,7 +1031,7 @@ illegal_return: 
     * no change to exception level, execution state or stack pointer

     */

    env->pstate |= PSTATE_IL;

    env->pc = env->elr_el[cur_el];

    env->pc = new_pc;

    spsr &= PSTATE_NZCV | PSTATE_DAIF;

    spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);

    pstate_write(env, spsr);

target/arm/helper-a64.h

+1 −1
Original line number Diff line number Diff line
@@ -86,7 +86,7 @@ DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) 
DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)

DEF_HELPER_2(sqrt_f16, f16, f16, ptr)



DEF_HELPER_1(exception_return, void, env)

DEF_HELPER_2(exception_return, void, env, i64)



DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64)

DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64)

target/arm/translate-a64.c

+6 −1
Original line number Diff line number Diff line
@@ -1981,6 +1981,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) 
static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)

{

    unsigned int opc, op2, op3, rn, op4;

    TCGv_i64 dst;



    opc = extract32(insn, 21, 4);

    op2 = extract32(insn, 16, 5);
@@ -2011,7 +2012,11 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) 
        if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {

            gen_io_start();

        }

        gen_helper_exception_return(cpu_env);

        dst = tcg_temp_new_i64();

        tcg_gen_ld_i64(dst, cpu_env,

                       offsetof(CPUARMState, elr_el[s->current_el]));

        gen_helper_exception_return(cpu_env, dst);

        tcg_temp_free_i64(dst);

        if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {

            gen_io_end();

        }