Commit d8b86898 authored by Richard Henderson's avatar Richard Henderson Committed by David Gibson
Browse files

target/ppc: Tidy gen_conditional_store 



Leave only the minimal amount of code within the STCX macro,
moving the rest of the code into gen_conditional_store.
Remove the explicit call to gen_check_align; the matching LDAX will
have already checked alignment, and we verify the same address.

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 14db1899

target/ppc/translate.c

+11 −17
Original line number Diff line number Diff line
@@ -3201,14 +3201,17 @@ ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) 
ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64)

#endif



static void gen_conditional_store(DisasContext *ctx, TCGv EA,

                                  int reg, int memop)

static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop)

{

    TCGLabel *l1 = gen_new_label();

    TCGLabel *l2 = gen_new_label();

    TCGv t0;

    TCGv t0 = tcg_temp_new();

    int reg = rS(ctx->opcode);



    tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);

    gen_set_access_type(ctx, ACCESS_RES);

    gen_addr_reg_index(ctx, t0);

    tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);

    tcg_temp_free(t0);



    t0 = tcg_temp_new();

    tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
@@ -3235,16 +3238,7 @@ static void gen_conditional_store(DisasContext *ctx, TCGv EA, 
#define STCX(name, memop)                  \

static void gen_##name(DisasContext *ctx)  \

{                                          \

    TCGv t0;                                                \

    int len = MEMOP_GET_SIZE(memop);                        \

    gen_set_access_type(ctx, ACCESS_RES);                   \

    t0 = tcg_temp_local_new();                              \

    gen_addr_reg_index(ctx, t0);                            \

    if (len > 1) {                                          \

        gen_check_align(ctx, t0, (len) - 1);                \

    }                                                       \

    gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \

    tcg_temp_free(t0);                                      \

    gen_conditional_store(ctx, memop);     \

}



STCX(stbcx_, DEF_MEMOP(MO_UB))