Commit d784733b authored by Corey Wharton's avatar Corey Wharton Committed by Alistair Francis
Browse files

target/riscv: Add a sifive-e34 cpu type 



The sifive-e34 cpu type is the same as the sifive-e31 with the
single precision floating-point extension enabled.

Signed-off-by: default avatarCorey Wharton <coreyw7@fb.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarBin Meng <bmeng.cn@gmail.com>
Message-id: 20200313193429.8035-3-coreyw7@fb.com
Message-Id: <20200313193429.8035-3-coreyw7@fb.com>
Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
parent 74dbba9b

target/riscv/cpu.c

+10 −0
Original line number Diff line number Diff line
@@ -164,6 +164,15 @@ static void rv32imacu_nommu_cpu_init(Object *obj) 
    set_feature(env, RISCV_FEATURE_PMP);

}



static void rv32imafcu_nommu_cpu_init(Object *obj)

{

    CPURISCVState *env = &RISCV_CPU(obj)->env;

    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);

    set_priv_version(env, PRIV_VERSION_1_10_0);

    set_resetvec(env, DEFAULT_RSTVEC);

    set_feature(env, RISCV_FEATURE_PMP);

}



#elif defined(TARGET_RISCV64)



static void riscv_base64_cpu_init(Object *obj)
@@ -610,6 +619,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { 
#if defined(TARGET_RISCV32)

    DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base32_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32imacu_nommu_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32imafcu_nommu_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init),

    /* Depreacted */

    DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU,  rv32imacu_nommu_cpu_init),

target/riscv/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ 
#define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")

#define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")

#define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")

#define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")

#define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")

#define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")

#define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")