Commit d5fdf9e9 authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Convert Neon fp VMAX/VMIN/VMAXNM/VMINNM/VRECPS/VRSQRTS to decodetree 



Convert the Neon fp VMAX/VMIN/VMAXNM/VMINNM/VRECPS/VRSQRTS 3-reg-same
insns to decodetree. (These are all the remaining non-accumulation
instructions in this group.)

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20200512163904.10918-17-peter.maydell@linaro.org
parent 26c6f695

target/arm/neon-dp.decode

+6 −0
Original line number Diff line number Diff line
@@ -188,5 +188,11 @@ VCGE_fp_3s 1111 001 1 0 . 0 . .... .... 1110 ... 0 .... @3same_fp 
VACGE_fp_3s      1111 001 1 0 . 0 . .... .... 1110 ... 1 .... @3same_fp

VCGT_fp_3s       1111 001 1 0 . 1 . .... .... 1110 ... 0 .... @3same_fp

VACGT_fp_3s      1111 001 1 0 . 1 . .... .... 1110 ... 1 .... @3same_fp

VMAX_fp_3s       1111 001 0 0 . 0 . .... .... 1111 ... 0 .... @3same_fp

VMIN_fp_3s       1111 001 0 0 . 1 . .... .... 1111 ... 0 .... @3same_fp

VPMAX_fp_3s      1111 001 1 0 . 0 . .... .... 1111 ... 0 .... @3same_fp_q0

VPMIN_fp_3s      1111 001 1 0 . 1 . .... .... 1111 ... 0 .... @3same_fp_q0

VRECPS_fp_3s     1111 001 0 0 . 0 . .... .... 1111 ... 1 .... @3same_fp

VRSQRTS_fp_3s    1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp

VMAXNM_fp_3s     1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp

VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp

target/arm/translate-neon.inc.c

+70 −0
Original line number Diff line number Diff line
@@ -1119,6 +1119,8 @@ DO_3S_FP(VCGE, gen_helper_neon_cge_f32, false) 
DO_3S_FP(VCGT, gen_helper_neon_cgt_f32, false)

DO_3S_FP(VACGE, gen_helper_neon_acge_f32, false)

DO_3S_FP(VACGT, gen_helper_neon_acgt_f32, false)

DO_3S_FP(VMAX, gen_helper_vfp_maxs, false)

DO_3S_FP(VMIN, gen_helper_vfp_mins, false)



static void gen_VMLA_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm,

                            TCGv_ptr fpstatus)
@@ -1137,6 +1139,74 @@ static void gen_VMLS_fp_3s(TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, 
DO_3S_FP(VMLA, gen_VMLA_fp_3s, true)

DO_3S_FP(VMLS, gen_VMLS_fp_3s, true)



static bool trans_VMAXNM_fp_3s(DisasContext *s, arg_3same *a)

{

    if (!arm_dc_feature(s, ARM_FEATURE_V8)) {

        return false;

    }



    if (a->size != 0) {

        /* TODO fp16 support */

        return false;

    }



    return do_3same_fp(s, a, gen_helper_vfp_maxnums, false);

}



static bool trans_VMINNM_fp_3s(DisasContext *s, arg_3same *a)

{

    if (!arm_dc_feature(s, ARM_FEATURE_V8)) {

        return false;

    }



    if (a->size != 0) {

        /* TODO fp16 support */

        return false;

    }



    return do_3same_fp(s, a, gen_helper_vfp_minnums, false);

}



WRAP_ENV_FN(gen_VRECPS_tramp, gen_helper_recps_f32)



static void gen_VRECPS_fp_3s(unsigned vece, uint32_t rd_ofs,

                             uint32_t rn_ofs, uint32_t rm_ofs,

                             uint32_t oprsz, uint32_t maxsz)

{

    static const GVecGen3 ops = { .fni4 = gen_VRECPS_tramp };

    tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops);

}



static bool trans_VRECPS_fp_3s(DisasContext *s, arg_3same *a)

{

    if (a->size != 0) {

        /* TODO fp16 support */

        return false;

    }



    return do_3same(s, a, gen_VRECPS_fp_3s);

}



WRAP_ENV_FN(gen_VRSQRTS_tramp, gen_helper_rsqrts_f32)



static void gen_VRSQRTS_fp_3s(unsigned vece, uint32_t rd_ofs,

                              uint32_t rn_ofs, uint32_t rm_ofs,

                              uint32_t oprsz, uint32_t maxsz)

{

    static const GVecGen3 ops = { .fni4 = gen_VRSQRTS_tramp };

    tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops);

}



static bool trans_VRSQRTS_fp_3s(DisasContext *s, arg_3same *a)

{

    if (a->size != 0) {

        /* TODO fp16 support */

        return false;

    }



    return do_3same(s, a, gen_VRSQRTS_fp_3s);

}



static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn)

{

    /* FP operations handled pairwise 32 bits at a time */

target/arm/translate.c

+2 −40
Original line number Diff line number Diff line
@@ -5436,6 +5436,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) 
        case NEON_3R_FLOAT_MULTIPLY:

        case NEON_3R_FLOAT_CMP:

        case NEON_3R_FLOAT_ACMP:

        case NEON_3R_FLOAT_MINMAX:

        case NEON_3R_FLOAT_MISC:

            /* Already handled by decodetree */

            return 1;

        }
@@ -5445,17 +5447,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) 
            return 1;

        }

        switch (op) {

        case NEON_3R_FLOAT_MINMAX:

            if (u) {

                return 1; /* VPMIN/VPMAX handled by decodetree */

            }

            break;

        case NEON_3R_FLOAT_MISC:

            /* VMAXNM/VMINNM in ARMv8 */

            if (u && !arm_dc_feature(s, ARM_FEATURE_V8)) {

                return 1;

            }

            break;

        case NEON_3R_VFM_VQRDMLSH:

            if (!dc_isar_feature(aa32_simdfmac, s)) {

                return 1;
@@ -5471,35 +5462,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) 
        tmp = neon_load_reg(rn, pass);

        tmp2 = neon_load_reg(rm, pass);

        switch (op) {

        case NEON_3R_FLOAT_MINMAX:

        {

            TCGv_ptr fpstatus = get_fpstatus_ptr(1);

            if (size == 0) {

                gen_helper_vfp_maxs(tmp, tmp, tmp2, fpstatus);

            } else {

                gen_helper_vfp_mins(tmp, tmp, tmp2, fpstatus);

            }

            tcg_temp_free_ptr(fpstatus);

            break;

        }

        case NEON_3R_FLOAT_MISC:

            if (u) {

                /* VMAXNM/VMINNM */

                TCGv_ptr fpstatus = get_fpstatus_ptr(1);

                if (size == 0) {

                    gen_helper_vfp_maxnums(tmp, tmp, tmp2, fpstatus);

                } else {

                    gen_helper_vfp_minnums(tmp, tmp, tmp2, fpstatus);

                }

                tcg_temp_free_ptr(fpstatus);

            } else {

                if (size == 0) {

                    gen_helper_recps_f32(tmp, cpu_env, tmp, tmp2);

                } else {

                    gen_helper_rsqrts_f32(tmp, cpu_env, tmp, tmp2);

              }

            }

            break;

        case NEON_3R_VFM_VQRDMLSH:

        {

            /* VFMA, VFMS: fused multiply-add */