Commit d5eaec84 authored by Max Filippov's avatar Max Filippov
Browse files

target/xtensa: regenerate and re-import test_mmuhifi_c3 core 



Overlay part of the test_mmuhifi_c3 core has GPL3 copyright headers in
it. Fix that by regenerating test_mmuhifi_c3 core overlay and
re-importing it.

Fixes: d848ea77 ("target/xtensa: add test_mmuhifi_c3 core")
Reported-by: default avatarThomas Huth <thuth@redhat.com>
Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
parent a30cb4b1

target/xtensa/core-test_mmuhifi_c3.c

+1 −2
Original line number Diff line number Diff line
@@ -27,8 +27,8 @@ 


#include "qemu/osdep.h"

#include "cpu.h"

#include "exec/exec-all.h"

#include "exec/gdbstub.h"

#include "qemu-common.h"

#include "qemu/host-utils.h"



#include "core-test_mmuhifi_c3/core-isa.h"
@@ -39,7 +39,6 @@ 


static XtensaConfig test_mmuhifi_c3 __attribute__((unused)) = {

    .name = "test_mmuhifi_c3",

    .options = XTENSA_OPTIONS,

    .gdb_regmap = {

        .reg = {

#include "core-test_mmuhifi_c3/gdb-config.inc.c"

target/xtensa/core-test_mmuhifi_c3/core-isa.h

+103 −13
Original line number Diff line number Diff line 
/*

 * Xtensa processor core configuration information.

 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa

 *				processor CORE configuration

 *

 * This file is subject to the terms and conditions of version 2.1 of the GNU

 * Lesser General Public License as published by the Free Software Foundation.

 *

 * Copyright (c) 1999-2009 Tensilica Inc.

 *  See <xtensa/config/core.h>, which includes this file, for more details.

 */



/* Xtensa processor core configuration information.



   Copyright (c) 1999-2019 Tensilica Inc.



   Permission is hereby granted, free of charge, to any person obtaining

   a copy of this software and associated documentation files (the

   "Software"), to deal in the Software without restriction, including

   without limitation the rights to use, copy, modify, merge, publish,

   distribute, sublicense, and/or sell copies of the Software, and to

   permit persons to whom the Software is furnished to do so, subject to

   the following conditions:



   The above copyright notice and this permission notice shall be included

   in all copies or substantial portions of the Software.



   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY

   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */



#ifndef XTENSA_CORE_TEST_MMUHIFI_C3_CORE_ISA_H

#define XTENSA_CORE_TEST_MMUHIFI_C3_CORE_ISA_H





/****************************************************************************

	    Parameters Useful for Any Code, USER or PRIVILEGED

 ****************************************************************************/
@@ -32,6 +54,7 @@ 
#define XCHAL_HAVE_DEBUG		1	/* debug option */

#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */

#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */

#define XCHAL_LOOP_BUFFER_SIZE		0	/* zero-ov. loop instr buffer size */

#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */

#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */

#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
@@ -59,44 +82,73 @@ 
#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */

#define XCHAL_HAVE_PRID			1	/* processor ID register */

#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */

#define XCHAL_HAVE_MX			1	/* MX core (Tensilica internal) */

#define XCHAL_HAVE_MP_INTERRUPTS	1	/* interrupt distributor port */

#define XCHAL_HAVE_MP_RUNSTALL		1	/* core RunStall control port */

#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */

#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */

#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */

#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */

#define XCHAL_HAVE_BOOLEANS		1	/* boolean registers */

#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */

#define XCHAL_CP_MAXCFG			2	/* max allowed cp id plus one */

#define XCHAL_HAVE_MAC16		0	/* MAC16 package */

#define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */

#define XCHAL_HAVE_FP			0	/* floating point pkg */

#define XCHAL_HAVE_FP			0	/* single prec floating point */

#define XCHAL_HAVE_FP_DIV		0	/* FP with DIV instructions */

#define XCHAL_HAVE_FP_RECIP		0	/* FP with RECIP instructions */

#define XCHAL_HAVE_FP_SQRT		0	/* FP with SQRT instructions */

#define XCHAL_HAVE_FP_RSQRT		0	/* FP with RSQRT instructions */

#define XCHAL_HAVE_DFP			0	/* double precision FP pkg */

#define XCHAL_HAVE_DFP_DIV		0	/* DFP with DIV instructions */

#define XCHAL_HAVE_DFP_RECIP		0	/* DFP with RECIP instructions*/

#define XCHAL_HAVE_DFP_SQRT		0	/* DFP with SQRT instructions */

#define XCHAL_HAVE_DFP_RSQRT		0	/* DFP with RSQRT instructions*/

#define XCHAL_HAVE_DFP_accel		0	/* double precision FP acceleration pkg */

#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */

#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */

#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */

#define XCHAL_HAVE_HIFI3		0	/* HiFi3 Audio Engine pkg */

#define XCHAL_HAVE_HIFI2		1	/* HiFi2 Audio Engine pkg */

#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */

#define XCHAL_HAVE_HIFI_MINI		0	

#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */

#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */

#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */

#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */

#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */

#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */

#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */

#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */

#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */

#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */

#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */

#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */

#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */





/*----------------------------------------------------------------------

				MISC

  ----------------------------------------------------------------------*/



#define XCHAL_NUM_LOADSTORE_UNITS	1	/* load/store units */

#define XCHAL_NUM_WRITEBUFFER_ENTRIES	8	/* size of write buffer */

#define XCHAL_INST_FETCH_WIDTH		8	/* instr-fetch width in bytes */

#define XCHAL_DATA_WIDTH		8	/* data width in bytes */

#define XCHAL_DATA_PIPE_DELAY		1	/* d-side pipeline delay

						   (1 = 5-stage, 2 = 7-stage) */

/*  In T1050, applies to selected core load and store instructions (see ISA): */

#define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */

#define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/

#define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */

#define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/



#define XCHAL_SW_VERSION		800000	/* sw version of this header */

#define XCHAL_SW_VERSION		1000006	/* sw version of this header */



#define XCHAL_CORE_ID			"test_mmuhifi_c3"	/* alphanum core name

						   (CoreID) set in the Xtensa

						   Processor Generator */



#define XCHAL_CORE_DESCRIPTION		"test_mmuhifi_c3"

#define XCHAL_BUILD_UNIQUE_ID		0x00005A6A	/* 22-bit sw build ID */



/*
@@ -136,6 +188,10 @@ 
#define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */

#define XCHAL_DCACHE_IS_COHERENT	1	/* MP coherence feature */



#define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */

#define XCHAL_HAVE_PREFETCH_L1		0	/* prefetch to L1 dcache */

#define XCHAL_PREFETCH_CASTOUT_LINES	0	/* dcache pref. castout bufsz */
@@ -172,6 +228,8 @@ 
#define XCHAL_ICACHE_ACCESS_SIZE	8

#define XCHAL_DCACHE_ACCESS_SIZE	8



#define XCHAL_DCACHE_BANKS		1	/* number of banks */



/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */

#define XCHAL_CA_BITS			4
@@ -187,6 +245,8 @@ 
#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/

#define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */



#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/





/*----------------------------------------------------------------------

			INTERRUPTS and TIMERS
@@ -261,6 +321,7 @@ 
#define XCHAL_INTTYPE_MASK_TIMER	0x00000140

#define XCHAL_INTTYPE_MASK_NMI		0x00000000

#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000

#define XCHAL_INTTYPE_MASK_PROFILING	0x00000000



/*  Interrupt numbers assigned to specific interrupt sources:  */

#define XCHAL_TIMER0_INTERRUPT		6	/* CCOMPARE0 */
@@ -273,7 +334,7 @@ 




/*

 *  External interrupt vectors/levels.

 *  External interrupt mapping.

 *  These macros describe how Xtensa processor interrupt numbers

 *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)

 *  map to external BInterrupt<n> pins, for those interrupts
@@ -281,7 +342,7 @@ 
 *  See the Xtensa processor databook for more details.

 */



/*  Core interrupt numbers mapped to each EXTERNAL interrupt number:  */

/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */

#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */

#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */

#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
@@ -291,6 +352,16 @@ 
#define XCHAL_EXTINT6_NUM		9	/* (intlevel 1) */

#define XCHAL_EXTINT7_NUM		10	/* (intlevel 1) */

#define XCHAL_EXTINT8_NUM		11	/* (intlevel 1) */

/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */

#define XCHAL_INT0_EXTNUM		0	/* (intlevel 1) */

#define XCHAL_INT1_EXTNUM		1	/* (intlevel 1) */

#define XCHAL_INT2_EXTNUM		2	/* (intlevel 1) */

#define XCHAL_INT3_EXTNUM		3	/* (intlevel 1) */

#define XCHAL_INT4_EXTNUM		4	/* (intlevel 1) */

#define XCHAL_INT5_EXTNUM		5	/* (intlevel 1) */

#define XCHAL_INT9_EXTNUM		6	/* (intlevel 1) */

#define XCHAL_INT10_EXTNUM		7	/* (intlevel 1) */

#define XCHAL_INT11_EXTNUM		8	/* (intlevel 1) */





/*----------------------------------------------------------------------
@@ -300,11 +371,13 @@ 
#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture

						   number: 1 == XEA1 (old)

							   2 == XEA2 (new)

							   0 == XEAX (extern) */

							   0 == XEAX (extern) or TX */

#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */

#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */

#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */

#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */

#define XCHAL_HAVE_HALT			0	/* halt architecture option */

#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */

#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */

#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */

#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
@@ -344,13 +417,30 @@ 




/*----------------------------------------------------------------------

				DEBUG

				DEBUG MODULE

  ----------------------------------------------------------------------*/



/*  Misc  */

#define XCHAL_HAVE_DEBUG_ERI		0	/* ERI to debug module */

#define XCHAL_HAVE_DEBUG_APB		0	/* APB to debug module */

#define XCHAL_HAVE_DEBUG_JTAG		0	/* JTAG to debug module */



/*  On-Chip Debug (OCD)  */

#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */

#define XCHAL_NUM_IBREAK		0	/* number of IBREAKn regs */

#define XCHAL_NUM_DBREAK		0	/* number of DBREAKn regs */

#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option */

#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */

#define XCHAL_HAVE_OCD_LS32DDR		0	/* L32DDR/S32DDR (faster OCD) */



/*  TRAX (in core)  */

#define XCHAL_HAVE_TRAX			0	/* TRAX in debug module */

#define XCHAL_TRAX_MEM_SIZE		0	/* TRAX memory size in bytes */

#define XCHAL_TRAX_MEM_SHAREABLE	0	/* start/end regs; ready sig. */

#define XCHAL_TRAX_ATB_WIDTH		0	/* ATB width (bits), 0=no ATB */

#define XCHAL_TRAX_TIME_WIDTH		0	/* timestamp bitwidth, 0=none */



/*  Perf counters  */

#define XCHAL_NUM_PERF_COUNTERS		0	/* performance counters */





/*----------------------------------------------------------------------

target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c

+97 −17
Original line number Diff line number Diff line 
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.



   Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.

   Copyright (c) 2003-2019 Tensilica Inc.



   This file is part of GDB.

   Permission is hereby granted, free of charge, to any person obtaining

   a copy of this software and associated documentation files (the

   "Software"), to deal in the Software without restriction, including

   without limitation the rights to use, copy, modify, merge, publish,

   distribute, sublicense, and/or sell copies of the Software, and to

   permit persons to whom the Software is furnished to do so, subject to

   the following conditions:



   This program is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3 of the License, or

   (at your option) any later version.

   The above copyright notice and this permission notice shall be included

   in all copies or substantial portions of the Software.



   This program is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   GNU General Public License for more details.



   You should have received a copy of the GNU General Public License

   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */



  /*    idx ofs bi sz al targno  flags cp typ group name  */

   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY

   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */

  XTREG(  0,  0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc,          0,0,0,0,0,0)

  XTREG(  1,  4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0,         0,0,0,0,0,0)

  XTREG(  2,  8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1,         0,0,0,0,0,0)
@@ -58,8 +60,8 @@ 
  XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase,     0,0,0,0,0,0)

  XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase,  0,0,0,0,0,0)

  XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)

  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176,       0,0,0,0,0,0)

  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208,       0,0,0,0,0,0)

  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)

  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)

  XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps,          0,0,0,0,0,0)

  XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr,   0,0,0,0,0,0)

  XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br,          0,0,0,0,0,0)
@@ -137,4 +139,82 @@ 
  XTREG(104,464,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13,         0,0,0,0,0,0)

  XTREG(105,468,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14,         0,0,0,0,0,0)

  XTREG(106,472,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15,         0,0,0,0,0,0)

  XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,

            0,0,&xtensa_mask0,0,0,0)

  XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,

            0,0,&xtensa_mask1,0,0,0)

  XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,

            0,0,&xtensa_mask2,0,0,0)

  XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,

            0,0,&xtensa_mask3,0,0,0)

  XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,

            0,0,&xtensa_mask4,0,0,0)

  XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,

            0,0,&xtensa_mask5,0,0,0)

  XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,

            0,0,&xtensa_mask6,0,0,0)

  XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,

            0,0,&xtensa_mask7,0,0,0)

  XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,

            0,0,&xtensa_mask8,0,0,0)

  XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,

            0,0,&xtensa_mask9,0,0,0)

  XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,

            0,0,&xtensa_mask10,0,0,0)

  XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,

            0,0,&xtensa_mask11,0,0,0)

  XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,

            0,0,&xtensa_mask12,0,0,0)

  XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,

            0,0,&xtensa_mask13,0,0,0)

  XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,

            0,0,&xtensa_mask14,0,0,0)

  XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,

            0,0,&xtensa_mask15,0,0,0)

  XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel,

            0,0,&xtensa_mask16,0,0,0)

  XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum,

            0,0,&xtensa_mask17,0,0,0)

  XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe,

            0,0,&xtensa_mask18,0,0,0)

  XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring,

            0,0,&xtensa_mask19,0,0,0)

  XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm,

            0,0,&xtensa_mask20,0,0,0)

  XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc,

            0,0,&xtensa_mask21,0,0,0)

  XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb,

            0,0,&xtensa_mask22,0,0,0)

  XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr,

            0,0,&xtensa_mask23,0,0,0)

  XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben,

            0,0,&xtensa_mask24,0,0,0)

  XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum,

            0,0,&xtensa_mask25,0,0,0)

  XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3,

            0,0,&xtensa_mask26,0,0,0)

  XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2,

            0,0,&xtensa_mask27,0,0,0)

  XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1,

            0,0,&xtensa_mask28,0,0,0)

  XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4,

            0,0,&xtensa_mask29,0,0,0)

  XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4,

            0,0,&xtensa_mask30,0,0,0)

  XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase,

            0,0,&xtensa_mask31,0,0,0)

  XTREG(139,556, 1, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_overflow,

            0,0,&xtensa_mask32,0,0,0)

  XTREG(140,560, 6, 4, 4,0x201b,0x0006, 1, 5,0x1010,ae_sar,

            0,0,&xtensa_mask33,0,0,0)

  XTREG(141,564, 4, 4, 4,0x201c,0x0006, 1, 5,0x1010,ae_bitptr,

            0,0,&xtensa_mask34,0,0,0)

  XTREG(142,568, 4, 4, 4,0x201d,0x0006, 1, 5,0x1010,ae_bitsused,

            0,0,&xtensa_mask35,0,0,0)

  XTREG(143,572, 4, 4, 4,0x201e,0x0006, 1, 5,0x1010,ae_tablesize,

            0,0,&xtensa_mask36,0,0,0)

  XTREG(144,576, 4, 4, 4,0x201f,0x0006, 1, 5,0x1010,ae_first_ts,

            0,0,&xtensa_mask37,0,0,0)

  XTREG(145,580,27, 4, 4,0x2020,0x0006, 1, 5,0x1010,ae_nextoffset,

            0,0,&xtensa_mask38,0,0,0)

  XTREG_END

target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c

+3184 −3200

File changed.

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