Commit d5d680ca authored by Tony Nguyen's avatar Tony Nguyen Committed by Richard Henderson
Browse files

memory: Access MemoryRegion with endianness 



Preparation for collapsing the two byte swaps adjust_endianness and
handle_bswap into the former.

Call memory_region_dispatch_{read|write} with endianness encoded into
the "MemOp op" operand.

This patch does not change any behaviour as
memory_region_dispatch_{read|write} is yet to handle the endianness.

Once it does handle endianness, callers with byte swaps can collapse
them into adjust_endianness.

Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarTony Nguyen <tony.nguyen@bt.com>
Message-Id: <8066ab3eb037c0388dfadfe53c5118429dd1de3a.1566466906.git.tony.nguyen@bt.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent 07f0834f

accel/tcg/cputlb.c

+6 −2
Original line number Diff line number Diff line
@@ -906,7 +906,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, 
        qemu_mutex_lock_iothread();

        locked = true;

    }

    r = memory_region_dispatch_read(mr, mr_offset, &val, size_memop(size),

    r = memory_region_dispatch_read(mr, mr_offset, &val,

                                    size_memop(size) | MO_TE,

                                    iotlbentry->attrs);

    if (r != MEMTX_OK) {

        hwaddr physaddr = mr_offset +
@@ -947,7 +948,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, 
        qemu_mutex_lock_iothread();

        locked = true;

    }

    r = memory_region_dispatch_write(mr, mr_offset, val, size_memop(size),

    r = memory_region_dispatch_write(mr, mr_offset, val,

                                     size_memop(size) | MO_TE,

                                     iotlbentry->attrs);

    if (r != MEMTX_OK) {

        hwaddr physaddr = mr_offset +
@@ -1305,6 +1307,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, 
            }

        }



        /* TODO: Merge bswap into io_readx -> memory_region_dispatch_read.  */

        res = io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index],

                       mmu_idx, addr, retaddr, access_type, size);

        return handle_bswap(res, size, big_endian);
@@ -1553,6 +1556,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, 
            }

        }



        /* TODO: Merge bswap into io_writex -> memory_region_dispatch_write.  */

        io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx,

                  handle_bswap(val, size, big_endian),

                  addr, retaddr, size);

exec.c

+11 −2
Original line number Diff line number Diff line
@@ -3364,8 +3364,13 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, 
            /* XXX: could force current_cpu to NULL to avoid

               potential bugs */

            val = ldn_p(buf, l);

            /*

             * TODO: Merge bswap from ldn_p into memory_region_dispatch_write

             * by using ldn_he_p and dropping MO_TE to get a host-endian value.

             */

            result |= memory_region_dispatch_write(mr, addr1, val,

                                                   size_memop(l), attrs);

                                                   size_memop(l) | MO_TE,

                                                   attrs);

        } else {

            /* RAM case */

            ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
@@ -3426,8 +3431,12 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, 
            /* I/O case */

            release_lock |= prepare_mmio_access(mr);

            l = memory_access_size(mr, l, addr1);

            /*

             * TODO: Merge bswap from stn_p into memory_region_dispatch_read

             * by using stn_he_p and dropping MO_TE to get a host-endian value.

             */

            result |= memory_region_dispatch_read(mr, addr1, &val,

                                                  size_memop(l), attrs);

                                                  size_memop(l) | MO_TE, attrs);

            stn_p(buf, l, val);

        } else {

            /* RAM case */

hw/intc/armv7m_nvic.c

+8 −7
Original line number Diff line number Diff line
@@ -2349,8 +2349,8 @@ static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr, 
    if (attrs.secure) {

        /* S accesses to the alias act like NS accesses to the real region */

        attrs.secure = 0;

        return memory_region_dispatch_write(mr, addr, value, size_memop(size),

                                            attrs);

        return memory_region_dispatch_write(mr, addr, value,

                                            size_memop(size) | MO_TE, attrs);

    } else {

        /* NS attrs are RAZ/WI for privileged, and BusFault for user */

        if (attrs.user) {
@@ -2369,8 +2369,8 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr, 
    if (attrs.secure) {

        /* S accesses to the alias act like NS accesses to the real region */

        attrs.secure = 0;

        return memory_region_dispatch_read(mr, addr, data, size_memop(size),

                                           attrs);

        return memory_region_dispatch_read(mr, addr, data,

                                           size_memop(size) | MO_TE, attrs);

    } else {

        /* NS attrs are RAZ/WI for privileged, and BusFault for user */

        if (attrs.user) {
@@ -2396,8 +2396,8 @@ static MemTxResult nvic_systick_write(void *opaque, hwaddr addr, 


    /* Direct the access to the correct systick */

    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);

    return memory_region_dispatch_write(mr, addr, value, size_memop(size),

                                        attrs);

    return memory_region_dispatch_write(mr, addr, value,

                                        size_memop(size) | MO_TE, attrs);

}



static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,
@@ -2409,7 +2409,8 @@ static MemTxResult nvic_systick_read(void *opaque, hwaddr addr, 


    /* Direct the access to the correct systick */

    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);

    return memory_region_dispatch_read(mr, addr, data, size_memop(size), attrs);

    return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE,

                                       attrs);

}



static const MemoryRegionOps nvic_systick_ops = {

hw/s390x/s390-pci-inst.c

+4 −2
Original line number Diff line number Diff line
@@ -373,7 +373,8 @@ static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias, 
    mr = pbdev->pdev->io_regions[pcias].memory;

    mr = s390_get_subregion(mr, offset, len);

    offset -= mr->addr;

    return memory_region_dispatch_read(mr, offset, data, size_memop(len),

    return memory_region_dispatch_read(mr, offset, data,

                                       size_memop(len) | MO_BE,

                                       MEMTXATTRS_UNSPECIFIED);

}
@@ -472,7 +473,8 @@ static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias, 
    mr = pbdev->pdev->io_regions[pcias].memory;

    mr = s390_get_subregion(mr, offset, len);

    offset -= mr->addr;

    return memory_region_dispatch_write(mr, offset, data, size_memop(len),

    return memory_region_dispatch_write(mr, offset, data,

                                        size_memop(len) | MO_BE,

                                        MEMTXATTRS_UNSPECIFIED);

}

hw/vfio/pci-quirks.c

+3 −2
Original line number Diff line number Diff line
@@ -1074,7 +1074,8 @@ static void vfio_rtl8168_quirk_address_write(void *opaque, hwaddr addr, 


                /* Write to the proper guest MSI-X table instead */

                memory_region_dispatch_write(&vdev->pdev.msix_table_mmio,

                                             offset, val, size_memop(size),

                                             offset, val,

                                             size_memop(size) | MO_LE,

                                             MEMTXATTRS_UNSPECIFIED);

            }

            return; /* Do not write guest MSI-X data to hardware */
@@ -1105,7 +1106,7 @@ static uint64_t vfio_rtl8168_quirk_data_read(void *opaque, 
    if (rtl->enabled && (vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX)) {

        hwaddr offset = rtl->addr & 0xfff;

        memory_region_dispatch_read(&vdev->pdev.msix_table_mmio, offset,

                                    &data, size_memop(size),

                                    &data, size_memop(size) | MO_LE,

                                    MEMTXATTRS_UNSPECIFIED);

        trace_vfio_quirk_rtl8168_msix_read(vdev->vbasedev.name, offset, data);

    }