Commit d49e8a9b authored by Cédric Le Goater's avatar Cédric Le Goater Committed by David Gibson
Browse files

ppc: Reset the interrupt presenter from the CPU reset handler 



On the sPAPR machine and PowerNV machine, the interrupt presenters are
created by a machine handler at the core level and are reset
independently. This is not consistent and it raises issues when it
comes to handle hot-plugged CPUs. In that case, the presenters are not
reset. This is less of an issue in XICS, although a zero MFFR could
be a concern, but in XIVE, the OS CAM line is not set and this breaks
the presenting algorithm. The current code has workarounds which need
a global cleanup.

Extend the sPAPR IRQ backend and the PowerNV Chip class with a new
cpu_intc_reset() handler called by the CPU reset handler and remove
the XiveTCTX reset handler which is now redundant.

Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Message-Id: <20191022163812.330-6-clg@kaod.org>
Reviewed-by: default avatarGreg Kurz <groug@kaod.org>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent aa5ac64b

hw/intc/spapr_xive.c

+9 −0
Original line number Diff line number Diff line
@@ -553,6 +553,14 @@ static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 
    return 0;

}



static void spapr_xive_cpu_intc_reset(SpaprInterruptController *intc,

                                     PowerPCCPU *cpu)

{

    XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx;



    xive_tctx_reset(tctx);

}



static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val)

{

    SpaprXive *xive = SPAPR_XIVE(intc);
@@ -697,6 +705,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data) 
    sicc->activate = spapr_xive_activate;

    sicc->deactivate = spapr_xive_deactivate;

    sicc->cpu_intc_create = spapr_xive_cpu_intc_create;

    sicc->cpu_intc_reset = spapr_xive_cpu_intc_reset;

    sicc->claim_irq = spapr_xive_claim_irq;

    sicc->free_irq = spapr_xive_free_irq;

    sicc->set_irq = spapr_xive_set_irq;

hw/intc/xics.c

+2 −6
Original line number Diff line number Diff line
@@ -274,10 +274,8 @@ static const VMStateDescription vmstate_icp_server = { 
    },

};



static void icp_reset_handler(void *dev)

void icp_reset(ICPState *icp)

{

    ICPState *icp = ICP(dev);



    icp->xirr = 0;

    icp->pending_priority = 0xff;

    icp->mfrr = 0xff;
@@ -288,7 +286,7 @@ static void icp_reset_handler(void *dev) 
    if (kvm_irqchip_in_kernel()) {

        Error *local_err = NULL;



        icp_set_kvm_state(ICP(dev), &local_err);

        icp_set_kvm_state(icp, &local_err);

        if (local_err) {

            error_report_err(local_err);

        }
@@ -351,7 +349,6 @@ static void icp_realize(DeviceState *dev, Error **errp) 
        }

    }



    qemu_register_reset(icp_reset_handler, dev);

    vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);

}
@@ -360,7 +357,6 @@ static void icp_unrealize(DeviceState *dev, Error **errp) 
    ICPState *icp = ICP(dev);



    vmstate_unregister(NULL, &vmstate_icp_server, icp);

    qemu_unregister_reset(icp_reset_handler, dev);

}



static void icp_class_init(ObjectClass *klass, void *data)

hw/intc/xics_spapr.c

+7 −0
Original line number Diff line number Diff line
@@ -346,6 +346,12 @@ static int xics_spapr_cpu_intc_create(SpaprInterruptController *intc, 
    return 0;

}



static void xics_spapr_cpu_intc_reset(SpaprInterruptController *intc,

                                     PowerPCCPU *cpu)

{

    icp_reset(spapr_cpu_state(cpu)->icp);

}



static int xics_spapr_claim_irq(SpaprInterruptController *intc, int irq,

                                bool lsi, Error **errp)

{
@@ -433,6 +439,7 @@ static void ics_spapr_class_init(ObjectClass *klass, void *data) 
    sicc->activate = xics_spapr_activate;

    sicc->deactivate = xics_spapr_deactivate;

    sicc->cpu_intc_create = xics_spapr_cpu_intc_create;

    sicc->cpu_intc_reset = xics_spapr_cpu_intc_reset;

    sicc->claim_irq = xics_spapr_claim_irq;

    sicc->free_irq = xics_spapr_free_irq;

    sicc->set_irq = xics_spapr_set_irq;

hw/intc/xive.c

+1 −11
Original line number Diff line number Diff line
@@ -547,10 +547,8 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon) 
    }

}



static void xive_tctx_reset(void *dev)

void xive_tctx_reset(XiveTCTX *tctx)

{

    XiveTCTX *tctx = XIVE_TCTX(dev);



    memset(tctx->regs, 0, sizeof(tctx->regs));



    /* Set some defaults */
@@ -607,13 +605,6 @@ static void xive_tctx_realize(DeviceState *dev, Error **errp) 
            return;

        }

    }



    qemu_register_reset(xive_tctx_reset, dev);

}



static void xive_tctx_unrealize(DeviceState *dev, Error **errp)

{

    qemu_unregister_reset(xive_tctx_reset, dev);

}



static int vmstate_xive_tctx_pre_save(void *opaque)
@@ -668,7 +659,6 @@ static void xive_tctx_class_init(ObjectClass *klass, void *data) 


    dc->desc = "XIVE Interrupt Thread Context";

    dc->realize = xive_tctx_realize;

    dc->unrealize = xive_tctx_unrealize;

    dc->vmsd = &vmstate_xive_tctx;

    /*

     * Reason: part of XIVE interrupt controller, needs to be wired up

hw/ppc/pnv.c

+18 −0
Original line number Diff line number Diff line
@@ -778,6 +778,13 @@ static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 
    pnv_cpu->intc = obj;

}



static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)

{

    PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);



    icp_reset(ICP(pnv_cpu->intc));

}



/*

 *    0:48  Reserved - Read as zeroes

 *   49:52  Node ID
@@ -815,6 +822,13 @@ static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 
    pnv_cpu->intc = obj;

}



static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)

{

    PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);



    xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));

}



/*

 * Allowed core identifiers on a POWER8 Processor Chip :

 *
@@ -984,6 +998,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 
    k->cores_mask = POWER8E_CORE_MASK;

    k->core_pir = pnv_chip_core_pir_p8;

    k->intc_create = pnv_chip_power8_intc_create;

    k->intc_reset = pnv_chip_power8_intc_reset;

    k->isa_create = pnv_chip_power8_isa_create;

    k->dt_populate = pnv_chip_power8_dt_populate;

    k->pic_print_info = pnv_chip_power8_pic_print_info;
@@ -1003,6 +1018,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 
    k->cores_mask = POWER8_CORE_MASK;

    k->core_pir = pnv_chip_core_pir_p8;

    k->intc_create = pnv_chip_power8_intc_create;

    k->intc_reset = pnv_chip_power8_intc_reset;

    k->isa_create = pnv_chip_power8_isa_create;

    k->dt_populate = pnv_chip_power8_dt_populate;

    k->pic_print_info = pnv_chip_power8_pic_print_info;
@@ -1022,6 +1038,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 
    k->cores_mask = POWER8_CORE_MASK;

    k->core_pir = pnv_chip_core_pir_p8;

    k->intc_create = pnv_chip_power8_intc_create;

    k->intc_reset = pnv_chip_power8_intc_reset;

    k->isa_create = pnv_chip_power8nvl_isa_create;

    k->dt_populate = pnv_chip_power8_dt_populate;

    k->pic_print_info = pnv_chip_power8_pic_print_info;
@@ -1191,6 +1208,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 
    k->cores_mask = POWER9_CORE_MASK;

    k->core_pir = pnv_chip_core_pir_p9;

    k->intc_create = pnv_chip_power9_intc_create;

    k->intc_reset = pnv_chip_power9_intc_reset;

    k->isa_create = pnv_chip_power9_isa_create;

    k->dt_populate = pnv_chip_power9_dt_populate;

    k->pic_print_info = pnv_chip_power9_pic_print_info;