Loading tcg/mips/tcg-target.inc.c +24 −23 Original line number Diff line number Diff line Loading @@ -195,11 +195,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch(*ct_str++) { case 'r': ct->ct |= TCG_CT_REG; tcg_regset_set(ct->u.regs, 0xffffffff); ct->u.regs = 0xffffffff; break; case 'L': /* qemu_ld input arg constraint */ ct->ct |= TCG_CT_REG; tcg_regset_set(ct->u.regs, 0xffffffff); ct->u.regs = 0xffffffff; tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); #if defined(CONFIG_SOFTMMU) if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { Loading @@ -209,7 +209,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, break; case 'S': /* qemu_st constraint */ ct->ct |= TCG_CT_REG; tcg_regset_set(ct->u.regs, 0xffffffff); ct->u.regs = 0xffffffff; tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); #if defined(CONFIG_SOFTMMU) if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { Loading Loading @@ -2607,27 +2607,28 @@ static void tcg_target_qemu_prologue(TCGContext *s) static void tcg_target_init(TCGContext *s) { tcg_target_detect_isa(); tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], 0xffffffff); tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; if (TCG_TARGET_REG_BITS == 64) { tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64], 0xffffffff); } tcg_regset_set(tcg_target_call_clobber_regs, (1 << TCG_REG_V0) | (1 << TCG_REG_V1) | (1 << TCG_REG_A0) | (1 << TCG_REG_A1) | (1 << TCG_REG_A2) | (1 << TCG_REG_A3) | (1 << TCG_REG_T0) | (1 << TCG_REG_T1) | (1 << TCG_REG_T2) | (1 << TCG_REG_T3) | (1 << TCG_REG_T4) | (1 << TCG_REG_T5) | (1 << TCG_REG_T6) | (1 << TCG_REG_T7) | (1 << TCG_REG_T8) | (1 << TCG_REG_T9)); tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; } tcg_target_call_clobber_regs = 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); s->reserved_regs = 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ Loading tcg/tcg.c +4 −4 Original line number Diff line number Diff line Loading @@ -2362,7 +2362,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def, TCGTemp *ts, *ots; TCGType otype, itype; tcg_regset_set(allocated_regs, s->reserved_regs); allocated_regs = s->reserved_regs; ots = &s->temps[args[0]]; ts = &s->temps[args[1]]; Loading Loading @@ -2450,8 +2450,8 @@ static void tcg_reg_alloc_op(TCGContext *s, args + nb_oargs + nb_iargs, sizeof(TCGArg) * def->nb_cargs); tcg_regset_set(i_allocated_regs, s->reserved_regs); tcg_regset_set(o_allocated_regs, s->reserved_regs); i_allocated_regs = s->reserved_regs; o_allocated_regs = s->reserved_regs; /* satisfy input constraints */ for(k = 0; k < nb_iargs; k++) { Loading Loading @@ -2651,7 +2651,7 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs, } /* assign input registers */ tcg_regset_set(allocated_regs, s->reserved_regs); allocated_regs = s->reserved_regs; for(i = 0; i < nb_regs; i++) { arg = args[nb_oargs + i]; if (arg != TCG_CALL_DUMMY_ARG) { Loading tcg/tcg.h +0 −1 Original line number Diff line number Diff line Loading @@ -186,7 +186,6 @@ typedef enum TCGOpcode { NB_OPS, } TCGOpcode; #define tcg_regset_set(d, s) (d) = (s) #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg) #define tcg_regset_set_reg(d, r) (d) |= 1L << (r) #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r)) Loading Loading
tcg/mips/tcg-target.inc.c +24 −23 Original line number Diff line number Diff line Loading @@ -195,11 +195,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch(*ct_str++) { case 'r': ct->ct |= TCG_CT_REG; tcg_regset_set(ct->u.regs, 0xffffffff); ct->u.regs = 0xffffffff; break; case 'L': /* qemu_ld input arg constraint */ ct->ct |= TCG_CT_REG; tcg_regset_set(ct->u.regs, 0xffffffff); ct->u.regs = 0xffffffff; tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); #if defined(CONFIG_SOFTMMU) if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { Loading @@ -209,7 +209,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, break; case 'S': /* qemu_st constraint */ ct->ct |= TCG_CT_REG; tcg_regset_set(ct->u.regs, 0xffffffff); ct->u.regs = 0xffffffff; tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); #if defined(CONFIG_SOFTMMU) if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { Loading Loading @@ -2607,27 +2607,28 @@ static void tcg_target_qemu_prologue(TCGContext *s) static void tcg_target_init(TCGContext *s) { tcg_target_detect_isa(); tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], 0xffffffff); tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; if (TCG_TARGET_REG_BITS == 64) { tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64], 0xffffffff); } tcg_regset_set(tcg_target_call_clobber_regs, (1 << TCG_REG_V0) | (1 << TCG_REG_V1) | (1 << TCG_REG_A0) | (1 << TCG_REG_A1) | (1 << TCG_REG_A2) | (1 << TCG_REG_A3) | (1 << TCG_REG_T0) | (1 << TCG_REG_T1) | (1 << TCG_REG_T2) | (1 << TCG_REG_T3) | (1 << TCG_REG_T4) | (1 << TCG_REG_T5) | (1 << TCG_REG_T6) | (1 << TCG_REG_T7) | (1 << TCG_REG_T8) | (1 << TCG_REG_T9)); tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; } tcg_target_call_clobber_regs = 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); s->reserved_regs = 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ Loading
tcg/tcg.c +4 −4 Original line number Diff line number Diff line Loading @@ -2362,7 +2362,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def, TCGTemp *ts, *ots; TCGType otype, itype; tcg_regset_set(allocated_regs, s->reserved_regs); allocated_regs = s->reserved_regs; ots = &s->temps[args[0]]; ts = &s->temps[args[1]]; Loading Loading @@ -2450,8 +2450,8 @@ static void tcg_reg_alloc_op(TCGContext *s, args + nb_oargs + nb_iargs, sizeof(TCGArg) * def->nb_cargs); tcg_regset_set(i_allocated_regs, s->reserved_regs); tcg_regset_set(o_allocated_regs, s->reserved_regs); i_allocated_regs = s->reserved_regs; o_allocated_regs = s->reserved_regs; /* satisfy input constraints */ for(k = 0; k < nb_iargs; k++) { Loading Loading @@ -2651,7 +2651,7 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs, } /* assign input registers */ tcg_regset_set(allocated_regs, s->reserved_regs); allocated_regs = s->reserved_regs; for(i = 0; i < nb_regs; i++) { arg = args[nb_oargs + i]; if (arg != TCG_CALL_DUMMY_ARG) { Loading
tcg/tcg.h +0 −1 Original line number Diff line number Diff line Loading @@ -186,7 +186,6 @@ typedef enum TCGOpcode { NB_OPS, } TCGOpcode; #define tcg_regset_set(d, s) (d) = (s) #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg) #define tcg_regset_set_reg(d, r) (d) |= 1L << (r) #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r)) Loading