Commit d208ac0c authored by Leon Alrae's avatar Leon Alrae
Browse files

target-mips: generate fences 



Make use of memory barrier TCG opcode in MIPS front end.

Signed-off-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
parent e9deaad8

target-mips/translate.c

+30 −2
Original line number Diff line number Diff line
@@ -13109,6 +13109,34 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, 
    tcg_temp_free(t1);

}









static void gen_sync(int stype)









{









    TCGBar tcg_mo = TCG_BAR_SC;

















    switch (stype) {









    case 0x4: /* SYNC_WMB */









        tcg_mo |= TCG_MO_ST_ST;









        break;









    case 0x10: /* SYNC_MB */









        tcg_mo |= TCG_MO_ALL;









        break;









    case 0x11: /* SYNC_ACQUIRE */









        tcg_mo |= TCG_MO_LD_LD | TCG_MO_LD_ST;









        break;









    case 0x12: /* SYNC_RELEASE */









        tcg_mo |= TCG_MO_ST_ST | TCG_MO_LD_ST;









        break;









    case 0x13: /* SYNC_RMB */









        tcg_mo |= TCG_MO_LD_LD;









        break;









    default:









        tcg_mo |= TCG_MO_ALL;









        break;









    }

















    tcg_gen_mb(tcg_mo);









}

















static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)









{









    int extension = (ctx->opcode >> 6) & 0x3f;








@@ -13384,7 +13412,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)







    case 0x2d:









        switch (minor) {









        case SYNC:









            /* NOP */









            gen_sync(extract32(ctx->opcode, 16, 5));









            break;









        case SYSCALL:









            generate_exception_end(ctx, EXCP_SYSCALL);








@@ -17201,7 +17229,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)







        break;









    case OPC_SYNC:









        check_insn(ctx, ISA_MIPS2);









        /* Treat as NOP. */









        gen_sync(extract32(ctx->opcode, 6, 5));









        break;

















#if defined(TARGET_MIPS64)