Commit d1b3b1ee authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-november-2018-v2' into staging 



MIPS queue for QEMU 3.1-rc2 - v2

# gpg: Signature made Sat 17 Nov 2018 18:30:46 GMT
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-november-2018-v2:
  MAINTAINERS: Add Stefan Markovic as a MIPS reviewer
  target/mips: Disable R5900 support
  target/mips: Rename MMI-related functions
  target/mips: Rename MMI-related opcodes
  target/mips: Rename MMI-related masks
  target/mips: Guard check_insn with INSN_R5900 check
  target/mips: Guard check_insn_opc_user_only with INSN_R5900 check
  target/mips: Fix decoding mechanism of special R5900 opcodes
  target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1
  target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1
  linux-user: Update MIPS specific prctl() implementation

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents d0649109 90b27c4c

MAINTAINERS

+9 −0
Original line number Diff line number Diff line
@@ -190,6 +190,7 @@ F: disas/microblaze.c 
MIPS

M: Aurelien Jarno <aurelien@aurel32.net>

M: Aleksandar Markovic <amarkovic@wavecomp.com>

R: Stefan Markovic <smarkovic@wavecomp.com>

S: Maintained

F: target/mips/

F: hw/mips/
@@ -336,6 +337,7 @@ F: target/arm/kvm.c 


MIPS

M: James Hogan <jhogan@kernel.org>

R: Stefan Markovic <smarkovic@wavecomp.com>

S: Maintained

F: target/mips/kvm.c
@@ -741,27 +743,32 @@ MIPS Machines 
-------------

Jazz

M: Hervé Poussineau <hpoussin@reactos.org>

R: Stefan Markovic <smarkovic@wavecomp.com>

S: Maintained

F: hw/mips/mips_jazz.c



Malta

M: Aurelien Jarno <aurelien@aurel32.net>

R: Stefan Markovic <smarkovic@wavecomp.com>

S: Maintained

F: hw/mips/mips_malta.c



Mipssim

M: Aleksandar Markovic <amarkovic@wavecomp.com>

R: Stefan Markovic <smarkovic@wavecomp.com>

S: Odd Fixes

F: hw/mips/mips_mipssim.c

F: hw/net/mipsnet.c



R4000

M: Aurelien Jarno <aurelien@aurel32.net>

R: Stefan Markovic <smarkovic@wavecomp.com>

S: Maintained

F: hw/mips/mips_r4k.c



Fulong 2E

M: Aleksandar Markovic <amarkovic@wavecomp.com>

R: Stefan Markovic <smarkovic@wavecomp.com>

S: Odd Fixes

F: hw/mips/mips_fulong2e.c

F: hw/isa/vt82c686.c
@@ -770,6 +777,7 @@ F: include/hw/isa/vt82c686.h 


Boston

M: Paul Burton <pburton@wavecomp.com>

R: Stefan Markovic <smarkovic@wavecomp.com>

S: Maintained

F: hw/core/loader-fit.c

F: hw/mips/boston.c
@@ -1992,6 +2000,7 @@ F: disas/i386.c 


MIPS target

M: Aurelien Jarno <aurelien@aurel32.net>

R: Stefan Markovic <smarkovic@wavecomp.com>

S: Maintained

F: tcg/mips/

F: disas/mips.c

linux-user/syscall.c

+18 −0
Original line number Diff line number Diff line
@@ -9554,9 +9554,25 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, 
        {

            CPUMIPSState *env = ((CPUMIPSState *)cpu_env);

            bool old_fr = env->CP0_Status & (1 << CP0St_FR);

            bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE);

            bool new_fr = arg2 & TARGET_PR_FP_MODE_FR;

            bool new_fre = arg2 & TARGET_PR_FP_MODE_FRE;



            const unsigned int known_bits = TARGET_PR_FP_MODE_FR |

                                            TARGET_PR_FP_MODE_FRE;



            /* If nothing to change, return right away, successfully.  */

            if (old_fr == new_fr && old_fre == new_fre) {

                return 0;

            }

            /* Check the value is valid */

            if (arg2 & ~known_bits) {

                return -TARGET_EOPNOTSUPP;

            }

            /* Setting FRE without FR is not supported.  */

            if (new_fre && !new_fr) {

                return -TARGET_EOPNOTSUPP;

            }

            if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) {

                /* FR1 is not supported */

                return -TARGET_EOPNOTSUPP;
@@ -9586,6 +9602,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, 
                env->hflags |= MIPS_HFLAG_F64;

            } else {

                env->CP0_Status &= ~(1 << CP0St_FR);

                env->hflags &= ~MIPS_HFLAG_F64;

            }

            if (new_fre) {

                env->CP0_Config5 |= (1 << CP0C5_FRE);
@@ -9594,6 +9611,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, 
                }

            } else {

                env->CP0_Config5 &= ~(1 << CP0C5_FRE);

                env->hflags &= ~MIPS_HFLAG_FRE;

            }



            return 0;

target/mips/translate.c

+423 −284

File changed.

Preview size limit exceeded, changes collapsed.

target/mips/translate_init.inc.c

+0 −59
Original line number Diff line number Diff line
@@ -410,65 +410,6 @@ const mips_def_t mips_defs[] = 
        .insn_flags = CPU_MIPS32R5 | ASE_MSA,

        .mmu_type = MMU_TYPE_R4000,

    },

    {

        /*

         * The Toshiba TX System RISC TX79 Core Architecture manual

         *

         * https://wiki.qemu.org/File:C790.pdf

         *

         * describes the C790 processor that is a follow-up to the R5900.

         * There are a few notable differences in that the R5900 FPU

         *

         * - is not IEEE 754-1985 compliant,

         * - does not implement double format, and

         * - its machine code is nonstandard.

         */

        .name = "R5900",

        .CP0_PRid = 0x00002E00,

        /* No L2 cache, icache size 32k, dcache size 32k, uncached coherency. */

        .CP0_Config0 = (0x3 << 9) | (0x3 << 6) | (0x2 << CP0C0_K0),

        .CP0_Status_rw_bitmask = 0xF4C79C1F,

#ifdef CONFIG_USER_ONLY

        /*

         * R5900 hardware traps to the Linux kernel for IEEE 754-1985 and LL/SC

         * emulation. For user only, QEMU is the kernel, so we emulate the traps

         * by simply emulating the instructions directly.

         *

         * Note: Config1 is only used internally, the R5900 has only Config0.

         */

        .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),

        .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,

        .CP0_LLAddr_shift = 4,

        .CP1_fcr0 = (0x38 << FCR0_PRID) | (0x0 << FCR0_REV),

        .CP1_fcr31 = 0,

        .CP1_fcr31_rw_bitmask = 0x0183FFFF,

#else

        /*

         * The R5900 COP1 FPU implements single-precision floating-point

         * operations but is not entirely IEEE 754-1985 compatible. In

         * particular,

         *

         * - NaN (not a number) and +/- infinities are not supported;

         * - exception mechanisms are not fully supported;

         * - denormalized numbers are not supported;

         * - rounding towards nearest and +/- infinities are not supported;

         * - computed results usually differs in the least significant bit;

         * - saturations can differ more than the least significant bit.

         *

         * Since only rounding towards zero is supported, the two least

         * significant bits of FCR31 are hardwired to 01.

         *

         * FPU emulation is disabled here until it is implemented.

         *

         * Note: Config1 is only used internally, the R5900 has only Config0.

         */

        .CP0_Config1 = (47 << CP0C1_MMU),

#endif /* !CONFIG_USER_ONLY */

        .SEGBITS = 32,

        .PABITS = 32,

        .insn_flags = CPU_R5900 | ASE_MMI,

        .mmu_type = MMU_TYPE_R4000,

    },

    {

        /* A generic CPU supporting MIPS32 Release 6 ISA.

           FIXME: Support IEEE 754-2008 FP.