Commit d19f1ab0 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200521-1' into staging 



target-arm queue:
 * tests/acceptance: Add a test for the canon-a1100 machine
 * docs/system: Document some of the Arm development boards
 * linux-user: make BKPT insn cause SIGTRAP, not be a syscall
 * target/arm: Remove unused GEN_NEON_INTEGER_OP macro
 * fsl-imx25, fsl-imx31, fsl-imx6, fsl-imx6ul, fsl-imx7: implement watchdog
 * hw/arm: Use qemu_log_mask() instead of hw_error() in various places
 * ARM: PL061: Introduce N_GPIOS
 * target/arm: Improve clear_vec_high() usage
 * target/arm: Allow user-mode code to write CPSR.E via MSR
 * linux-user/arm: Reset CPSR_E when entering a signal handler
 * linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32

# gpg: Signature made Thu 21 May 2020 22:05:48 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200521-1: (29 commits)
  linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
  linux-user/arm: Reset CPSR_E when entering a signal handler
  target/arm: Allow user-mode code to write CPSR.E via MSR
  target/arm: Use clear_vec_high more effectively
  target/arm: Use tcg_gen_gvec_mov for clear_vec_high
  ARM: PL061: Introduce N_GPIOS
  hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask()
  hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask()
  hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask()
  hw/arm/integratorcp: Replace hw_error() by qemu_log_mask()
  hw/arm/fsl-imx7: Connect watchdog interrupts
  hw/arm/fsl-imx7: Instantiate various unimplemented devices
  hw/arm/fsl-imx6ul: Connect watchdog interrupts
  hw/arm/fsl-imx6: Connect watchdog interrupts
  hw/arm/fsl-imx31: Wire up watchdog
  hw/arm/fsl-imx25: Wire up watchdog
  hw/watchdog: Implement full i.MX watchdog support
  hw: Move i.MX watchdog driver to hw/watchdog
  target/arm: Remove unused GEN_NEON_INTEGER_OP macro
  linux-user/arm: Fix identification of syscall numbers
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents ae3aa5da fafe7229

MAINTAINERS

+6 −0
Original line number Diff line number Diff line
@@ -608,6 +608,7 @@ S: Odd Fixes 
F: include/hw/arm/digic.h

F: hw/*/digic*

F: include/hw/*/digic*

F: tests/acceptance/machine_arm_canona1100.py



Goldfish RTC

M: Anup Patel <anup.patel@wdc.com>
@@ -632,8 +633,10 @@ S: Odd Fixes 
F: hw/arm/fsl-imx25.c

F: hw/arm/imx25_pdk.c

F: hw/misc/imx25_ccm.c

F: hw/watchdog/wdt_imx2.c

F: include/hw/arm/fsl-imx25.h

F: include/hw/misc/imx25_ccm.h

F: include/hw/watchdog/wdt_imx2.h



i.MX31 (kzm)

M: Peter Chubb <peter.chubb@nicta.com.au>
@@ -700,12 +703,14 @@ F: hw/misc/armsse-cpuid.c 
F: include/hw/misc/armsse-cpuid.h

F: hw/misc/armsse-mhu.c

F: include/hw/misc/armsse-mhu.h

F: docs/system/arm/mps2.rst



Musca

M: Peter Maydell <peter.maydell@linaro.org>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/arm/musca.c

F: docs/system/arm/musca.rst



Musicpal

M: Jan Kiszka <jan.kiszka@web.de>
@@ -827,6 +832,7 @@ M: Peter Maydell <peter.maydell@linaro.org> 
L: qemu-arm@nongnu.org

S: Maintained

F: hw/arm/vexpress.c

F: docs/system/arm/vexpress.rst



Versatile PB

M: Peter Maydell <peter.maydell@linaro.org>

docs/system/arm/integratorcp.rst

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Integrator/CP (``integratorcp``)

================================

Arm Integrator/CP (``integratorcp``)

====================================



The Arm Integrator/CP board is emulated with the following devices:

docs/system/arm/mps2.rst

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Arm MPS2 boards (``mps2-an385``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)

================================================================================



These board models all use Arm M-profile CPUs.



The Arm MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger

FPGA but is otherwise the same as the 2). Since the CPU itself

and most of the devices are in the FPGA, the details of the board

as seen by the guest depend significantly on the FPGA image.



QEMU models the following FPGA images:



``mps2-an385``

  Cortex-M3 as documented in ARM Application Note AN385

``mps2-an511``

  Cortex-M3 'DesignStart' as documented in AN511

``mps2-an505``

  Cortex-M33 as documented in ARM Application Note AN505

``mps2-an521``

  Dual Cortex-M33 as documented in Application Note AN521



Differences between QEMU and real hardware:



- AN385 remapping of low 16K of memory to either ZBT SSRAM1 or to

  block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as

  if zbt_boot_ctrl is always zero)

- QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest

  visible difference is that the LAN9118 doesn't support checksum

  offloading

docs/system/arm/musca.rst

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Arm Musca boards (``musca-a``, ``musca-b1``)

============================================



The Arm Musca development boards are a reference implementation

of a system using the SSE-200 Subsystem for Embedded. They are

dual Cortex-M33 systems.



QEMU provides models of the A and B1 variants of this board.



Unimplemented devices:



- SPI

- |I2C|

- |I2S|

- PWM

- QSPI

- Timer

- SCC

- GPIO

- eFlash

- MHU

- PVT

- SDIO

- CryptoCell



Note that (like the real hardware) the Musca-A machine is

asymmetric: CPU 0 does not have the FPU or DSP extensions,

but CPU 1 does. Also like the real hardware, the memory maps

for the A and B1 variants differ significantly, so guest

software must be built for the right variant.

docs/system/arm/vexpress.rst

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Arm Versatile Express boards (``vexpress-a9``, ``vexpress-a15``)

================================================================



QEMU models two variants of the Arm Versatile Express development

board family:



- ``vexpress-a9`` models the combination of the Versatile Express

  motherboard and the CoreTile Express A9x4 daughterboard

- ``vexpress-a15`` models the combination of the Versatile Express

  motherboard and the CoreTile Express A15x2 daughterboard



Note that as this hardware does not have PCI, IDE or SCSI,

the only available storage option is emulated SD card.



Implemented devices:



- PL041 audio

- PL181 SD controller

- PL050 keyboard and mouse

- PL011 UARTs

- SP804 timers

- I2C controller

- PL031 RTC

- PL111 LCD display controller

- Flash memory

- LAN9118 ethernet



Unimplemented devices:



- SP810 system control block

- PCI-express

- USB controller (Philips ISP1761)

- Local DAP ROM

- CoreSight interfaces

- PL301 AXI interconnect

- SCC

- System counter

- HDLCD controller (``vexpress-a15``)

- SP805 watchdog

- PL341 dynamic memory controller

- DMA330 DMA controller

- PL354 static memory controller

- BP147 TrustZone Protection Controller

- TrustZone Address Space Controller



Other differences between the hardware and the QEMU model:



- QEMU will default to creating one CPU unless you pass a different

  ``-smp`` argument

- QEMU allows the amount of RAM provided to be specified with the

  ``-m`` argument

- QEMU defaults to providing a CPU which does not provide either

  TrustZone or the Virtualization Extensions: if you want these you

  must enable them with ``-machine secure=on`` and ``-machine

  virtualization=on``

- QEMU provides 4 virtio-mmio virtio transports; these start at

  address ``0x10013000`` for ``vexpress-a9`` and at ``0x1c130000`` for

  ``vexpress-a15``, and have IRQs from 40 upwards. If a dtb is

  provided on the command line then QEMU will edit it to include

  suitable entries describing these transports for the guest.