Commit d19d1f96 authored by Daniel P. Berrangé's avatar Daniel P. Berrangé Committed by Eduardo Habkost
Browse files

i386: define the 'ssbd' CPUID feature bit (CVE-2018-3639) 



New microcode introduces the "Speculative Store Bypass Disable"
CPUID feature bit. This needs to be exposed to guest OS to allow
them to protect against CVE-2018-3639.

Signed-off-by: default avatarDaniel P. Berrangé <berrange@redhat.com>
Reviewed-by: default avatarKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: default avatarKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Message-Id: <20180521215424.13520-2-berrange@redhat.com>
Signed-off-by: default avatarEduardo Habkost <ehabkost@redhat.com>
parent 9802316e

target/i386/cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -805,7 +805,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 
            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, "spec-ctrl", NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, "ssbd",

        },

        .cpuid_eax = 7,

        .cpuid_needs_ecx = true, .cpuid_ecx = 0,

target/i386/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -685,6 +685,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */

#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */

#define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control */

#define CPUID_7_0_EDX_SPEC_CTRL_SSBD  (1U << 31) /* Speculative Store Bypass Disable */



#define KVM_HINTS_DEDICATED (1U << 0)