Commit d10eb08f authored by Alex Bennée's avatar Alex Bennée
Browse files

cputlb: drop flush_global flag from tlb_flush 



We have never has the concept of global TLB entries which would avoid
the flush so we never actually use this flag. Drop it and make clear
that tlb_flush is the sledge-hammer it has always been.

Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
[DG: ppc portions]
Acked-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent ba7d3d18

cputlb.c

+6 −15
Original line number Diff line number Diff line
@@ -60,24 +60,15 @@ 
/* statistics */

int tlb_flush_count;



/* NOTE:

 * If flush_global is true (the usual case), flush all tlb entries.

 * If flush_global is false, flush (at least) all tlb entries not

 * marked global.

 *

 * Since QEMU doesn't currently implement a global/not-global flag

 * for tlb entries, at the moment tlb_flush() will also flush all

 * tlb entries in the flush_global == false case. This is OK because

 * CPU architectures generally permit an implementation to drop

 * entries from the TLB at any time, so flushing more entries than

 * required is only an efficiency issue, not a correctness issue.

/* This is OK because CPU architectures generally permit an

 * implementation to drop entries from the TLB at any time, so

 * flushing more entries than required is only an efficiency issue,

 * not a correctness issue.

 */

void tlb_flush(CPUState *cpu, int flush_global)

void tlb_flush(CPUState *cpu)

{

    CPUArchState *env = cpu->env_ptr;



    tlb_debug("(%d)\n", flush_global);



    memset(env->tlb_table, -1, sizeof(env->tlb_table));

    memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table));

    memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
@@ -144,7 +135,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr) 
                  TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",

                  env->tlb_flush_addr, env->tlb_flush_mask);



        tlb_flush(cpu, 1);

        tlb_flush(cpu);

        return;

    }

exec.c

+2 −2
Original line number Diff line number Diff line
@@ -544,7 +544,7 @@ static int cpu_common_post_load(void *opaque, int version_id) 
    /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the

       version_id is increased. */

    cpu->interrupt_request &= ~0x01;

    tlb_flush(cpu, 1);

    tlb_flush(cpu);



    return 0;

}
@@ -2426,7 +2426,7 @@ static void tcg_commit(MemoryListener *listener) 
     */

    d = atomic_rcu_read(&cpuas->as->dispatch);

    atomic_rcu_set(&cpuas->memory_dispatch, d);

    tlb_flush(cpuas->cpu, 1);

    tlb_flush(cpuas->cpu);

}



void address_space_init_dispatch(AddressSpace *as)

hw/sh4/sh7750.c

+1 −1
Original line number Diff line number Diff line
@@ -417,7 +417,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr, 
    case SH7750_PTEH_A7:

        /* If asid changes, clear all registered tlb entries. */

        if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) {

            tlb_flush(CPU(s->cpu), 1);

            tlb_flush(CPU(s->cpu));

        }

        s->cpu->env.pteh = mem_value;

        return;

include/exec/exec-all.h

+6 −8
Original line number Diff line number Diff line
@@ -95,15 +95,13 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr); 
/**

 * tlb_flush:

 * @cpu: CPU whose TLB should be flushed

 * @flush_global: ignored

 *

 * Flush the entire TLB for the specified CPU.

 * The flush_global flag is in theory an indicator of whether the whole

 * TLB should be flushed, or only those entries not marked global.

 * In practice QEMU does not implement any global/not global flag for

 * TLB entries, and the argument is ignored.

 * Flush the entire TLB for the specified CPU. Most CPU architectures

 * allow the implementation to drop entries from the TLB at any time

 * so this is generally safe. If more selective flushing is required

 * use one of the other functions for efficiency.

 */

void tlb_flush(CPUState *cpu, int flush_global);

void tlb_flush(CPUState *cpu);

/**

 * tlb_flush_page_by_mmuidx:

 * @cpu: CPU whose TLB should be flushed
@@ -165,7 +163,7 @@ static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) 
{

}



static inline void tlb_flush(CPUState *cpu, int flush_global)

static inline void tlb_flush(CPUState *cpu)

{

}

target/alpha/cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -273,7 +273,7 @@ static void alpha_cpu_initfn(Object *obj) 
    CPUAlphaState *env = &cpu->env;



    cs->env_ptr = env;

    tlb_flush(cs, 1);

    tlb_flush(cs);



    alpha_translate_init();