Commit d0db7cad authored by Greg Kurz's avatar Greg Kurz Committed by David Gibson
Browse files

target/ppc: Consolidate 64-bit server processor detection in a helper 



We use PPC_SEGMENT_64B in various places to guard code that is specific
to 64-bit server processors compliant with arch 2.x. Consolidate the
logic in a helper macro with an explicit name.

Signed-off-by: default avatarGreg Kurz <groug@kaod.org>
Message-Id: <155327783157.1283071.3747129891004927299.stgit@bahia.lan>
Tested-by: default avatarSuraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent fa200c95

hw/ppc/ppc.c

+1 −1
Original line number Diff line number Diff line
@@ -1101,7 +1101,7 @@ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) 
    tb_env = g_malloc0(sizeof(ppc_tb_t));

    env->tb_env = tb_env;

    tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;

    if (env->insns_flags & PPC_SEGMENT_64B) {

    if (is_book3s_arch2x(env)) {

        /* All Book3S 64bit CPUs implement level based DEC logic */

        tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;

    }

target/ppc/cpu.h

+6 −0
Original line number Diff line number Diff line
@@ -2409,6 +2409,12 @@ enum { 
target_ulong cpu_read_xer(CPUPPCState *env);

void cpu_write_xer(CPUPPCState *env, target_ulong xer);



/*

 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,

 * have PPC_SEGMENT_64B.

 */

#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))



static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,

                                        target_ulong *cs_base, uint32_t *flags)

{

target/ppc/helper_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -152,7 +152,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, 
     * - 64-bit embedded implementations do not need any operation to be

     *   performed when PR is set.

     */

    if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) & 1)) {

    if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) {

        value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);

    }

#endif

target/ppc/translate.c

+4 −6
Original line number Diff line number Diff line
@@ -3755,7 +3755,7 @@ static void gen_bcond(DisasContext *ctx, int type) 
             * arch 2.x, do implement a "test and decrement" logic instead,

             * as described in their respective UMs.

             */

            if (unlikely(!(ctx->insns_flags & PPC_SEGMENT_64B))) {

            if (unlikely(!is_book3s_arch2x(ctx))) {

                gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);

                tcg_temp_free(temp);

                tcg_temp_free(target);
@@ -3913,7 +3913,7 @@ static void gen_rfi(DisasContext *ctx) 
    /* This instruction doesn't exist anymore on 64-bit server

     * processors compliant with arch 2.x

     */

    if (ctx->insns_flags & PPC_SEGMENT_64B) {

    if (is_book3s_arch2x(ctx)) {

        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);

        return;

    }
@@ -6535,8 +6535,7 @@ static void gen_msgclr(DisasContext *ctx) 
    GEN_PRIV;

#else

    CHK_HV;

    /* 64-bit server processors compliant with arch 2.x */

    if (ctx->insns_flags & PPC_SEGMENT_64B) {

    if (is_book3s_arch2x(ctx)) {

        gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);

    } else {

        gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
@@ -6550,8 +6549,7 @@ static void gen_msgsnd(DisasContext *ctx) 
    GEN_PRIV;

#else

    CHK_HV;

    /* 64-bit server processors compliant with arch 2.x */

    if (ctx->insns_flags & PPC_SEGMENT_64B) {

    if (is_book3s_arch2x(ctx)) {

        gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);

    } else {

        gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);