Commit ceffd34e authored by Rabin Vincent's avatar Rabin Vincent Committed by Edgar E. Iglesias
Browse files

target-cris: add v17 CPU 



In the CRIS v17 CPU an ADDC (add with carry) instruction has been added
compared to the v10 instruction set.

 Assembler syntax:

  ADDC [Rs],Rd
  ADDC [Rs+],Rd

 Size: Dword

 Description:

  The source data is added together with the carry flag to the
  destination register. The size of the operation is dword.

 Operation:

  Rd += s + C-flag;

 Flags affected:

  S R P U I X N Z V C
  - - - - - 0 * * * *

 Instruction format: ADDC [Rs],Rd

  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  |Destination(Rd)| 1   0   0   1   1   0   1   0 |   Source(Rs)  |
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

 Instruction format: ADDC [Rs+],Rd

  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  |Destination(Rd)| 1   1   0   1   1   0   1   0 |   Source(Rs)  |
  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

[EI: Shorten 80+ lines]
Reviewed-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: default avatarRabin Vincent <rabinv@axis.com>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
parent 17bc37b7

target-cris/cpu.c

+14 −0
Original line number Diff line number Diff line
@@ -246,6 +246,16 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data) 
    cc->gdb_read_register = crisv10_cpu_gdb_read_register;

}



static void crisv17_cpu_class_init(ObjectClass *oc, void *data)

{

    CPUClass *cc = CPU_CLASS(oc);

    CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);



    ccc->vr = 17;

    cc->do_interrupt = crisv10_cpu_do_interrupt;

    cc->gdb_read_register = crisv10_cpu_gdb_read_register;

}



static void crisv32_cpu_class_init(ObjectClass *oc, void *data)

{

    CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
@@ -272,6 +282,10 @@ static const TypeInfo cris_cpu_model_type_infos[] = { 
        .name = TYPE("crisv11"),

        .parent = TYPE_CRIS_CPU,

        .class_init = crisv11_cpu_class_init,

    }, {

        .name = TYPE("crisv17"),

        .parent = TYPE_CRIS_CPU,

        .class_init = crisv17_cpu_class_init,

    }, {

        .name = TYPE("crisv32"),

        .parent = TYPE_CRIS_CPU,

target-cris/crisv10-decode.h

+1 −0
Original line number Diff line number Diff line
@@ -92,6 +92,7 @@ 
#define CRISV10_IND_JUMP_M       4

#define CRISV10_IND_DIP          5

#define CRISV10_IND_JUMP_R       6

#define CRISV17_IND_ADDC         6

#define CRISV10_IND_BOUND        7

#define CRISV10_IND_BCC_M        7

#define CRISV10_IND_MOVE_M_SPR   8

target-cris/translate_v10.c

+23 −0
Original line number Diff line number Diff line
@@ -1094,6 +1094,29 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) 
                insn_len = dec10_bdap_m(env, dc, size);

                break;

            default:

            /*

             * ADDC for v17:

             *

             * Instruction format: ADDC [Rs],Rd

             *

             *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+

             *  |Destination(Rd)| 1   0   0   1   1   0   1   0 |   Source(Rs)|

             *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+

             *

             * Instruction format: ADDC [Rs+],Rd

             *

             *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+

             *  |Destination(Rd)| 1   1   0   1   1   0   1   0 |   Source(Rs)|

             *  +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+

             */

                if (dc->opcode == CRISV17_IND_ADDC && dc->size == 2 &&

                    env->pregs[PR_VR] == 17) {

                    LOG_DIS("addc op=%d %d\n",  dc->src, dc->dst);

                    cris_cc_mask(dc, CC_MASK_NZVC);

                    insn_len += dec10_ind_alu(env, dc, CC_OP_ADDC, size);

                    break;

                }



                LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",

                          dc->pc, size, dc->opcode, dc->src, dc->dst);

                cpu_abort(CPU(dc->cpu), "Unhandled opcode");