Commit ceecf1d1 authored by Aurelien Jarno's avatar Aurelien Jarno
Browse files

add an init function parameter to qemu_chr_open() 



And use it for the malta emulation. Fix segfault introduced in
revision 6352.

Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6365 c046a42c-6fe2-441c-8c8c-71466251a162
parent 9c554c1c

console.c

+2 −0
Original line number Diff line number Diff line
@@ -1357,6 +1357,8 @@ static void text_console_do_init(CharDriverState *chr, DisplayState *ds, const c 
    text_console_resize(s);



    qemu_chr_reset(chr);

    if (chr->init)

        chr->init(chr);

}



CharDriverState *text_console_init(const char *p)

gdbstub.c

+1 −1
Original line number Diff line number Diff line
@@ -2286,7 +2286,7 @@ int gdbserver_start(const char *port) 
        port = gdbstub_port_name;

    }



    chr = qemu_chr_open("gdb", port);

    chr = qemu_chr_open("gdb", port, NULL);

    if (!chr)

        return -1;

hw/mips_malta.c

+21 −14
Original line number Diff line number Diff line
@@ -418,7 +418,24 @@ static void malta_fpga_reset(void *opaque) 


    s->display_text[8] = '\0';

    snprintf(s->display_text, 9, "        ");

    malta_fpga_update_display(s);

}



static void malta_fpga_uart_init(CharDriverState *chr)

{

    qemu_chr_printf(chr, "CBUS UART\r\n");

}



static void malta_fpga_led_init(CharDriverState *chr)

{

    qemu_chr_printf(chr, "\e[HMalta LEDBAR\r\n");

    qemu_chr_printf(chr, "+--------+\r\n");

    qemu_chr_printf(chr, "+        +\r\n");

    qemu_chr_printf(chr, "+--------+\r\n");

    qemu_chr_printf(chr, "\n");

    qemu_chr_printf(chr, "Malta ASCII\r\n");

    qemu_chr_printf(chr, "+--------+\r\n");

    qemu_chr_printf(chr, "+        +\r\n");

    qemu_chr_printf(chr, "+--------+\r\n");

}



static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
@@ -436,19 +453,9 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env) 
    /* 0xa00 is less than a page, so will still get the right offsets.  */

    cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);



    s->display = qemu_chr_open("fpga", "vc:320x200");

    qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n");

    qemu_chr_printf(s->display, "+--------+\r\n");

    qemu_chr_printf(s->display, "+        +\r\n");

    qemu_chr_printf(s->display, "+--------+\r\n");

    qemu_chr_printf(s->display, "\n");

    qemu_chr_printf(s->display, "Malta ASCII\r\n");

    qemu_chr_printf(s->display, "+--------+\r\n");

    qemu_chr_printf(s->display, "+        +\r\n");

    qemu_chr_printf(s->display, "+--------+\r\n");



    uart_chr = qemu_chr_open("cbus", "vc:80Cx24C");

    qemu_chr_printf(uart_chr, "CBUS UART\r\n");

    s->display = qemu_chr_open("fpga", "vc:320x200", malta_fpga_led_init);



    uart_chr = qemu_chr_open("cbus", "vc:80Cx24C", malta_fpga_uart_init);

    s->uart =

        serial_mm_init(base + 0x900, 3, env->irq[2], 230400, uart_chr, 1);

hw/omap1.c

+2 −2
Original line number Diff line number Diff line
@@ -1988,7 +1988,7 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base, 
    s->fclk = fclk;

    s->irq = irq;

    s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,

                               chr ?: qemu_chr_open("null", "null"), 1);

                               chr ?: qemu_chr_open("null", "null", NULL), 1);



    return s;

}
@@ -2104,7 +2104,7 @@ void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr) 
    /* TODO: Should reuse or destroy current s->serial */

    s->serial = serial_mm_init(s->base, 2, s->irq,

                    omap_clk_getrate(s->fclk) / 16,

                    chr ?: qemu_chr_open("null", "null"), 1);

                    chr ?: qemu_chr_open("null", "null", NULL), 1);

}



/* MPU Clock/Reset/Power Mode Control */

hw/omap2.c

+1 −1
Original line number Diff line number Diff line
@@ -2161,7 +2161,7 @@ static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, 
    s->irq = irq;

    omap_sti_reset(s);



    s->chr = chr ?: qemu_chr_open("null", "null");

    s->chr = chr ?: qemu_chr_open("null", "null", NULL);



    iomemtype = l4_register_io_memory(0, omap_sti_readfn,

                    omap_sti_writefn, s);