Commit ce3960eb authored by Andreas Färber's avatar Andreas Färber
Browse files

cpu: Move nr_{cores,threads} fields to CPUState 



To facilitate the field movements, pass MIPSCPU to malta_mips_config();
avoid that for mips_cpu_map_tc() since callers only access MIPS Thread
Contexts, inside TCG helpers.

Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent cf7c3f0c

cpus.c

+2 −2
Original line number Diff line number Diff line
@@ -1041,8 +1041,8 @@ void qemu_init_vcpu(void *_env) 
    CPUArchState *env = _env;

    CPUState *cpu = ENV_GET_CPU(env);



    env->nr_cores = smp_cores;

    env->nr_threads = smp_threads;

    cpu->nr_cores = smp_cores;

    cpu->nr_threads = smp_threads;

    cpu->stopped = true;

    if (kvm_enabled()) {

        qemu_kvm_start_vcpu(env);

hw/mips_malta.c

+6 −3
Original line number Diff line number Diff line
@@ -743,10 +743,13 @@ static int64_t load_kernel (void) 
    return kernel_entry;

}



static void malta_mips_config(CPUMIPSState *env)

static void malta_mips_config(MIPSCPU *cpu)

{

    CPUMIPSState *env = &cpu->env;

    CPUState *cs = CPU(cpu);



    env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |

                         ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC);

                         ((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC);

}



static void main_cpu_reset(void *opaque)
@@ -763,7 +766,7 @@ static void main_cpu_reset(void *opaque) 
        env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));

    }



    malta_mips_config(env);

    malta_mips_config(cpu);

}



static void cpu_request_exit(void *opaque, int irq, int level)

include/exec/cpu-defs.h

+0 −2
Original line number Diff line number Diff line
@@ -196,8 +196,6 @@ typedef struct CPUWatchpoint { 
    int cpu_index; /* CPU index (informative) */                        \

    uint32_t host_tid; /* host thread ID */                             \

    int numa_node; /* NUMA node this cpu is belonging to  */            \

    int nr_cores;  /* number of cores within this CPU package */        \

    int nr_threads;/* number of threads within this CPU */              \

    int running; /* Nonzero if cpu is currently running(usermode).  */  \

    /* user data */                                                     \

    void *opaque;                                                       \

include/qom/cpu.h

+5 −0
Original line number Diff line number Diff line
@@ -57,6 +57,8 @@ struct kvm_run; 


/**

 * CPUState:

 * @nr_cores: Number of cores within this CPU package.

 * @nr_threads: Number of threads within this CPU.

 * @created: Indicates whether the CPU thread has been successfully created.

 * @stop: Indicates a pending stop request.

 * @stopped: Indicates the CPU has been artificially stopped.
@@ -69,6 +71,9 @@ struct CPUState { 
    DeviceState parent_obj;

    /*< public >*/



    int nr_cores;

    int nr_threads;



    struct QemuThread *thread;

#ifdef _WIN32

    HANDLE hThread;

target-i386/cpu.c

+9 −9
Original line number Diff line number Diff line
@@ -1691,8 +1691,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 
        *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */

        *ecx = env->cpuid_ext_features;

        *edx = env->cpuid_features;

        if (env->nr_cores * env->nr_threads > 1) {

            *ebx |= (env->nr_cores * env->nr_threads) << 16;

        if (cs->nr_cores * cs->nr_threads > 1) {

            *ebx |= (cs->nr_cores * cs->nr_threads) << 16;

            *edx |= 1 << 28;    /* HTT bit */

        }

        break;
@@ -1705,8 +1705,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 
        break;

    case 4:

        /* cache info: needed for Core compatibility */

        if (env->nr_cores > 1) {

            *eax = (env->nr_cores - 1) << 26;

        if (cs->nr_cores > 1) {

            *eax = (cs->nr_cores - 1) << 26;

        } else {

            *eax = 0;

        }
@@ -1725,8 +1725,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 
                break;

            case 2: /* L2 cache info */

                *eax |= 0x0000143;

                if (env->nr_threads > 1) {

                    *eax |= (env->nr_threads - 1) << 14;

                if (cs->nr_threads > 1) {

                    *eax |= (cs->nr_threads - 1) << 14;

                }

                *ebx = 0x3c0003f;

                *ecx = 0x0000fff;
@@ -1830,7 +1830,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 
         * discards multiple thread information if it is set.

         * So dont set it here for Intel to make Linux guests happy.

         */

        if (env->nr_cores * env->nr_threads > 1) {

        if (cs->nr_cores * cs->nr_threads > 1) {

            uint32_t tebx, tecx, tedx;

            get_cpuid_vendor(env, &tebx, &tecx, &tedx);

            if (tebx != CPUID_VENDOR_INTEL_1 ||
@@ -1878,8 +1878,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 
        *ebx = 0;

        *ecx = 0;

        *edx = 0;

        if (env->nr_cores * env->nr_threads > 1) {

            *ecx |= (env->nr_cores * env->nr_threads) - 1;

        if (cs->nr_cores * cs->nr_threads > 1) {

            *ecx |= (cs->nr_cores * cs->nr_threads) - 1;

        }

        break;

    case 0x8000000A: