Commit ce27c5d1 authored by Richard Henderson's avatar Richard Henderson
Browse files

tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded 



PowerPC Altivec does not support add and subtract of 64-bit elements.
Prepare for that configuration by not assuming the operation is
universally supported.

Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Reviewed-by: default avatarDavid Hildenbrand <david@redhat.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent ac383dde

tcg/tcg-op-vec.c

+33 −16
Original line number Diff line number Diff line
@@ -226,16 +226,6 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr b, TCGArg o, TCGType low_type) 
    vec_gen_3(INDEX_op_st_vec, low_type, 0, ri, bi, o);

}



void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)

{

    vec_gen_op3(INDEX_op_add_vec, vece, r, a, b);

}



void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)

{

    vec_gen_op3(INDEX_op_sub_vec, vece, r, a, b);

}



void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)

{

    vec_gen_op3(INDEX_op_and_vec, 0, r, a, b);
@@ -296,11 +286,30 @@ void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) 
    tcg_gen_not_vec(0, r, r);

}



void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a)

static bool do_op2(unsigned vece, TCGv_vec r, TCGv_vec a, TCGOpcode opc)

{

    if (TCG_TARGET_HAS_not_vec) {

        vec_gen_op2(INDEX_op_not_vec, 0, r, a);

    TCGTemp *rt = tcgv_vec_temp(r);

    TCGTemp *at = tcgv_vec_temp(a);

    TCGArg ri = temp_arg(rt);

    TCGArg ai = temp_arg(at);

    TCGType type = rt->base_type;

    int can;



    tcg_debug_assert(at->base_type >= type);

    can = tcg_can_emit_vec_op(opc, type, vece);

    if (can > 0) {

        vec_gen_2(opc, type, vece, ri, ai);

    } else if (can < 0) {

        tcg_expand_vec_op(opc, type, vece, ri, ai);

    } else {

        return false;

    }

    return true;

}



void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a)

{

    if (!TCG_TARGET_HAS_not_vec || !do_op2(vece, r, a, INDEX_op_not_vec)) {

        TCGv_vec t = tcg_const_ones_vec_matching(r);

        tcg_gen_xor_vec(0, r, a, t);

        tcg_temp_free_vec(t);
@@ -309,9 +318,7 @@ void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a) 


void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a)

{

    if (TCG_TARGET_HAS_neg_vec) {

        vec_gen_op2(INDEX_op_neg_vec, vece, r, a);

    } else {

    if (!TCG_TARGET_HAS_neg_vec || !do_op2(vece, r, a, INDEX_op_neg_vec)) {

        TCGv_vec t = tcg_const_zeros_vec_matching(r);

        tcg_gen_sub_vec(vece, r, t, a);

        tcg_temp_free_vec(t);
@@ -409,6 +416,16 @@ static void do_op3(unsigned vece, TCGv_vec r, TCGv_vec a, 
    }

}



void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)

{

    do_op3(vece, r, a, b, INDEX_op_add_vec);

}



void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)

{

    do_op3(vece, r, a, b, INDEX_op_sub_vec);

}



void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)

{

    do_op3(vece, r, a, b, INDEX_op_mul_vec);