Commit cd2d5541 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150212' into staging 



Convert to linked list.

# gpg: Signature made Fri 13 Feb 2015 05:40:41 GMT using RSA key ID 4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"

* remotes/rth/tags/pull-tcg-20150212:
  tcg: Remove unused opcodes
  tcg: Implement insert_op_before
  tcg: Remove opcodes instead of noping them out
  tcg: Put opcodes in a linked list
  tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
  tcg: Move emit of INDEX_op_end into gen_tb_end
  tcg: Reduce ifdefs in tcg-op.c
  tcg: Move some opcode generation functions out of line

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents e344e7af 15fc7daa

Makefile.target

+1 −1
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ all: $(PROGS) stap 
#########################################################

# cpu emulator library

obj-y = exec.o translate-all.o cpu-exec.o

obj-y += tcg/tcg.o tcg/optimize.o

obj-y += tcg/tcg.o tcg/tcg-op.o tcg/optimize.o

obj-$(CONFIG_TCG_INTERPRETER) += tci.o

obj-$(CONFIG_TCG_INTERPRETER) += disas/tci.o

obj-y += fpu/softfloat.o

include/exec/gen-icount.h

+17 −5
Original line number Diff line number Diff line
@@ -11,8 +11,8 @@ static int exitreq_label; 


static inline void gen_tb_start(TranslationBlock *tb)

{

    TCGv_i32 count;

    TCGv_i32 flag;

    TCGv_i32 count, flag, imm;

    int i;



    exitreq_label = gen_new_label();

    flag = tcg_temp_new_i32();
@@ -21,16 +21,25 @@ static inline void gen_tb_start(TranslationBlock *tb) 
    tcg_gen_brcondi_i32(TCG_COND_NE, flag, 0, exitreq_label);

    tcg_temp_free_i32(flag);



    if (!(tb->cflags & CF_USE_ICOUNT))

    if (!(tb->cflags & CF_USE_ICOUNT)) {

        return;

    }



    icount_label = gen_new_label();

    count = tcg_temp_local_new_i32();

    tcg_gen_ld_i32(count, cpu_env,

                   -ENV_OFFSET + offsetof(CPUState, icount_decr.u32));



    imm = tcg_temp_new_i32();

    tcg_gen_movi_i32(imm, 0xdeadbeef);



    /* This is a horrid hack to allow fixing up the value later.  */

    icount_arg = tcg_ctx.gen_opparam_ptr + 1;

    tcg_gen_subi_i32(count, count, 0xdeadbeef);

    i = tcg_ctx.gen_last_op_idx;

    i = tcg_ctx.gen_op_buf[i].args;

    icount_arg = &tcg_ctx.gen_opparam_buf[i + 1];



    tcg_gen_sub_i32(count, count, imm);

    tcg_temp_free_i32(imm);



    tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, icount_label);

    tcg_gen_st16_i32(count, cpu_env,
@@ -48,6 +57,9 @@ static void gen_tb_end(TranslationBlock *tb, int num_insns) 
        gen_set_label(icount_label);

        tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_ICOUNT_EXPIRED);

    }



    /* Terminate the linked list.  */

    tcg_ctx.gen_op_buf[tcg_ctx.gen_last_op_idx].next = -1;

}



static inline void gen_io_start(void)

target-alpha/translate.c

+8 −8
Original line number Diff line number Diff line
@@ -2790,7 +2790,6 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, 
    target_ulong pc_start;

    target_ulong pc_mask;

    uint32_t insn;

    uint16_t *gen_opc_end;

    CPUBreakpoint *bp;

    int j, lj = -1;

    ExitStatus ret;
@@ -2798,7 +2797,6 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, 
    int max_insns;



    pc_start = tb->pc;

    gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;



    ctx.tb = tb;

    ctx.pc = pc_start;
@@ -2839,12 +2837,13 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, 
            }

        }

        if (search_pc) {

            j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;

            j = tcg_op_buf_count();

            if (lj < j) {

                lj++;

                while (lj < j)

                while (lj < j) {

                    tcg_ctx.gen_opc_instr_start[lj++] = 0;

                }

            }

            tcg_ctx.gen_opc_pc[lj] = ctx.pc;

            tcg_ctx.gen_opc_instr_start[lj] = 1;

            tcg_ctx.gen_opc_icount[lj] = num_insns;
@@ -2881,7 +2880,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, 
           or exhaust instruction count, stop generation.  */

        if (ret == NO_EXIT

            && ((ctx.pc & pc_mask) == 0

                || tcg_ctx.gen_opc_ptr >= gen_opc_end

                || tcg_op_buf_full()

                || num_insns >= max_insns

                || singlestep

                || ctx.singlestep_enabled)) {
@@ -2912,12 +2911,13 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, 
    }



    gen_tb_end(tb, num_insns);

    *tcg_ctx.gen_opc_ptr = INDEX_op_end;



    if (search_pc) {

        j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;

        j = tcg_op_buf_count();

        lj++;

        while (lj <= j)

        while (lj <= j) {

            tcg_ctx.gen_opc_instr_start[lj++] = 0;

        }

    } else {

        tb->size = ctx.pc - pc_start;

        tb->icount = num_insns;

target-arm/translate-a64.c

+3 −7
Original line number Diff line number Diff line
@@ -10920,7 +10920,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, 
    CPUARMState *env = &cpu->env;

    DisasContext dc1, *dc = &dc1;

    CPUBreakpoint *bp;

    uint16_t *gen_opc_end;

    int j, lj;

    target_ulong pc_start;

    target_ulong next_page_start;
@@ -10931,8 +10930,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, 


    dc->tb = tb;



    gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;



    dc->is_jmp = DISAS_NEXT;

    dc->pc = pc_start;

    dc->singlestep_enabled = cs->singlestep_enabled;
@@ -11002,7 +10999,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, 
        }



        if (search_pc) {

            j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;

            j = tcg_op_buf_count();

            if (lj < j) {

                lj++;

                while (lj < j) {
@@ -11052,7 +11049,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, 
         * ensures prefetch aborts occur at the right place.

         */

        num_insns++;

    } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&

    } while (!dc->is_jmp && !tcg_op_buf_full() &&

             !cs->singlestep_enabled &&

             !singlestep &&

             !dc->ss_active &&
@@ -11112,7 +11109,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, 


done_generating:

    gen_tb_end(tb, num_insns);

    *tcg_ctx.gen_opc_ptr = INDEX_op_end;



#ifdef DEBUG_DISAS

    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
@@ -11124,7 +11120,7 @@ done_generating: 
    }

#endif

    if (search_pc) {

        j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;

        j = tcg_op_buf_count();

        lj++;

        while (lj <= j) {

            tcg_ctx.gen_opc_instr_start[lj++] = 0;

target-arm/translate.c

+3 −7
Original line number Diff line number Diff line
@@ -11025,7 +11025,6 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, 
    CPUARMState *env = &cpu->env;

    DisasContext dc1, *dc = &dc1;

    CPUBreakpoint *bp;

    uint16_t *gen_opc_end;

    int j, lj;

    target_ulong pc_start;

    target_ulong next_page_start;
@@ -11046,8 +11045,6 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, 


    dc->tb = tb;



    gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;



    dc->is_jmp = DISAS_NEXT;

    dc->pc = pc_start;

    dc->singlestep_enabled = cs->singlestep_enabled;
@@ -11182,7 +11179,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, 
            }

        }

        if (search_pc) {

            j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;

            j = tcg_op_buf_count();

            if (lj < j) {

                lj++;

                while (lj < j)
@@ -11248,7 +11245,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, 
         * Also stop translation when a page boundary is reached.  This

         * ensures prefetch aborts occur at the right place.  */

        num_insns ++;

    } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&

    } while (!dc->is_jmp && !tcg_op_buf_full() &&

             !cs->singlestep_enabled &&

             !singlestep &&

             !dc->ss_active &&
@@ -11357,7 +11354,6 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, 


done_generating:

    gen_tb_end(tb, num_insns);

    *tcg_ctx.gen_opc_ptr = INDEX_op_end;



#ifdef DEBUG_DISAS

    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
@@ -11369,7 +11365,7 @@ done_generating: 
    }

#endif

    if (search_pc) {

        j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;

        j = tcg_op_buf_count();

        lj++;

        while (lj <= j)

            tcg_ctx.gen_opc_instr_start[lj++] = 0;