Commit cd0c6f47 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by David Gibson
Browse files

ppc: Do some batching of TCG tlb flushes 



On ppc64 especially, we flush the tlb on any slbie or tlbie instruction.

However, those instructions often come in bursts of 3 or more (context
switch will favor a series of slbie's for example to an slbia if the
SLB has less than a certain number of entries in it, and tlbie's can
happen in a series, with PAPR, H_BULK_REMOVE can remove up to 4 entries
at a time.

Doing a tlb_flush() each time is a waste of time. We end up doing a memset
of the whole TLB, reloading it for the next instruction, memset'ing again,
etc...

Those instructions don't have to take effect immediately. For slbie, they
can wait for the next context synchronizing event. For tlbie, the next
tlbsync.

This implements batching by keeping a flag that indicates that we have a
TLB in need of flushing. We check it on interrupts, rfi's, isync's and
tlbsync and flush the TLB if needed.

This reduces the number of tlb_flush() on a boot to a ubuntu installer
first dialog screen from roughly 360K down to 36K.

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: added a 'CPUPPCState *' variable in h_remove() and
      h_bulk_remove() ]
Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
[dwg: removed spurious whitespace change, use 0/1 not true/false
      consistently, since tlb_need_flush has int type]
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 9fb04491

hw/ppc/spapr_hcall.c

+11 −3
Original line number Diff line number Diff line
@@ -186,6 +186,7 @@ static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, 
static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr,

                             target_ulong opcode, target_ulong *args)

{

    CPUPPCState *env = &cpu->env;

    target_ulong flags = args[0];

    target_ulong pte_index = args[1];

    target_ulong avpn = args[2];
@@ -196,6 +197,7 @@ static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 


    switch (ret) {

    case REMOVE_SUCCESS:

        check_tlb_flush(env);

        return H_SUCCESS;



    case REMOVE_NOT_FOUND:
@@ -232,7 +234,9 @@ static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 
static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr,

                                  target_ulong opcode, target_ulong *args)

{

    CPUPPCState *env = &cpu->env;

    int i;

    target_ulong rc = H_SUCCESS;



    for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) {

        target_ulong *tsh = &args[i*2];
@@ -265,14 +269,18 @@ static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 
            break;



        case REMOVE_PARM:

            return H_PARAMETER;

            rc = H_PARAMETER;

            goto exit;



        case REMOVE_HW:

            return H_HARDWARE;

            rc = H_HARDWARE;

            goto exit;

        }

    }

 exit:

    check_tlb_flush(env);



    return H_SUCCESS;

    return rc;

}



static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr,

target-ppc/cpu.h

+2 −0
Original line number Diff line number Diff line
@@ -958,6 +958,8 @@ struct CPUPPCState { 
    /* PowerPC 64 SLB area */

    ppc_slb_t slb[MAX_SLB_ENTRIES];

    int32_t slb_nr;

    /* tcg TLB needs flush (deferred slb inval instruction typically) */

    uint32_t tlb_need_flush;

#endif

    /* segment registers */

    hwaddr htab_base;

target-ppc/excp_helper.c

+8 −0
Original line number Diff line number Diff line
@@ -718,6 +718,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) 
    /* Reset exception state */

    cs->exception_index = POWERPC_EXCP_NONE;

    env->error_code = 0;



    /* Any interrupt is context synchronizing, check if TCG TLB

     * needs a delayed flush on ppc64

     */

    check_tlb_flush(env);

}



void ppc_cpu_do_interrupt(CPUState *cs)
@@ -943,6 +948,9 @@ static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr, 
     * as rfi is always the last insn of a TB

     */

    cs->interrupt_request |= CPU_INTERRUPT_EXITTB;



    /* Context synchronizing: check if TCG TLB needs flush */

    check_tlb_flush(env);

}



void helper_rfi(CPUPPCState *env)

target-ppc/helper.h

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ DEF_HELPER_1(rfmci, void, env) 
DEF_HELPER_1(rfid, void, env)

DEF_HELPER_1(hrfid, void, env)

#endif

DEF_HELPER_1(check_tlb_flush, void, env)

#endif



DEF_HELPER_3(lmw, void, env, tl, i32)

target-ppc/helper_regs.h

+13 −0
Original line number Diff line number Diff line
@@ -151,4 +151,17 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, 
    return excp;

}



#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)

static inline void check_tlb_flush(CPUPPCState *env)

{

    CPUState *cs = CPU(ppc_env_get_cpu(env));

    if (env->tlb_need_flush) {

        env->tlb_need_flush = 0;

        tlb_flush(cs, 1);

    }

}

#else

static inline void check_tlb_flush(CPUPPCState *env) { }

#endif



#endif /* !defined(__HELPER_REGS_H__) */