Commit ccb0c7e1 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150626' into staging 



MIPS patches 2015-06-26

Changes:
* MIPS UHI semihosting support
* microMIPS32 R6 support

# gpg: Signature made Fri Jun 26 10:42:33 2015 BST using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4  4FC0 5211 8E3C 0B29 DA6B

* remotes/lalrae/tags/mips-20150626:
  target-mips: add mips32r6-generic CPU definition
  target-mips: microMIPS32 R6 POOL16{A, C} instructions
  target-mips: microMIPS32 R6 Major instructions
  target-mips: microMIPS32 R6 POOL32{I, C} instructions
  target-mips: microMIPS32 R6 POOL32F instructions
  target-mips: microMIPS32 R6 POOL32A{XF} instructions
  target-mips: microMIPS32 R6 branches and jumps
  target-mips: add microMIPS32 R6 opcode enum
  target-mips: signal RI for removed instructions in microMIPS R6
  target-mips: raise RI exceptions when FIR.PS = 0
  target-mips: rearrange gen_compute_compact_branch
  target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP
  target-mips: remove an unused argument
  target-mips: add microMIPS TLBINV, TLBINVF
  target-mips: fix {RD, WR}PGPR in microMIPS
  target-mips: convert host to MIPS errno values when required
  target-mips: add Unified Hosting Interface (UHI) support
  target-mips: remove identical code in different branch
  hw/mips: Do not clear BEV for MIPS malta kernel load
  include/softmmu-semi.h: Make semihosting support 64-bit clean

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 0a4a0312 4b3bcd01

hw/mips/mips_malta.c

+9 −2
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ 
#include "qemu/error-report.h"

#include "hw/empty_slot.h"

#include "sysemu/kvm.h"

#include "exec/semihost.h"



//#define DEBUG_BOARD_INIT
@@ -634,7 +635,13 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base, 


    /* Second part of the bootloader */

    p = (uint32_t *) (base + 0x580);



    if (semihosting_get_argc()) {

        /* Preserve a0 content as arguments have been passed */

        stl_p(p++, 0x00000000);                         /* nop */

    } else {

        stl_p(p++, 0x24040002);                         /* addiu a0, zero, 2 */

    }

    stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */

    stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff));        /* ori sp, sp, low(ENVP_ADDR) */

    stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));       /* lui a1, high(ENVP_ADDR) */
@@ -887,7 +894,7 @@ static void main_cpu_reset(void *opaque) 
       read only location. The kernel location and the arguments table

       location does not change. */

    if (loaderparams.kernel_filename) {

        env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));

        env->CP0_Status &= ~(1 << CP0St_ERL);

    }



    malta_mips_config(cpu);

include/exec/softmmu-semi.h

+7 −6
Original line number Diff line number Diff line
@@ -9,14 +9,14 @@ 
#ifndef SOFTMMU_SEMI_H

#define SOFTMMU_SEMI_H 1



static inline uint32_t softmmu_tget32(CPUArchState *env, uint32_t addr)

static inline uint32_t softmmu_tget32(CPUArchState *env, target_ulong addr)

{

    uint32_t val;



    cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 0);

    return tswap32(val);

}

static inline uint32_t softmmu_tget8(CPUArchState *env, uint32_t addr)

static inline uint32_t softmmu_tget8(CPUArchState *env, target_ulong addr)

{

    uint8_t val;
@@ -28,7 +28,8 @@ static inline uint32_t softmmu_tget8(CPUArchState *env, uint32_t addr) 
#define get_user_u8(arg, p) ({ arg = softmmu_tget8(env, p) ; 0; })

#define get_user_ual(arg, p) get_user_u32(arg, p)



static inline void softmmu_tput32(CPUArchState *env, uint32_t addr, uint32_t val)

static inline void softmmu_tput32(CPUArchState *env,

                                  target_ulong addr, uint32_t val)

{

    val = tswap32(val);

    cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 1);
@@ -36,8 +37,8 @@ static inline void softmmu_tput32(CPUArchState *env, uint32_t addr, uint32_t val 
#define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; })

#define put_user_ual(arg, p) put_user_u32(arg, p)



static void *softmmu_lock_user(CPUArchState *env, uint32_t addr, uint32_t len,

                               int copy)

static void *softmmu_lock_user(CPUArchState *env,

                               target_ulong addr, target_ulong len, int copy)

{

    uint8_t *p;

    /* TODO: Make this something that isn't fixed size.  */
@@ -48,7 +49,7 @@ static void *softmmu_lock_user(CPUArchState *env, uint32_t addr, uint32_t len, 
    return p;

}

#define lock_user(type, p, len, copy) softmmu_lock_user(env, p, len, copy)

static char *softmmu_lock_user_string(CPUArchState *env, uint32_t addr)

static char *softmmu_lock_user_string(CPUArchState *env, target_ulong addr)

{

    char *p;

    char *s;

qemu-options.hx

+6 −4
Original line number Diff line number Diff line
@@ -3345,20 +3345,22 @@ Set OpenBIOS nvram @var{variable} to given @var{value} (PPC, SPARC only). 
ETEXI

DEF("semihosting", 0, QEMU_OPTION_semihosting,

    "-semihosting    semihosting mode\n",

    QEMU_ARCH_ARM | QEMU_ARCH_M68K | QEMU_ARCH_XTENSA | QEMU_ARCH_LM32)

    QEMU_ARCH_ARM | QEMU_ARCH_M68K | QEMU_ARCH_XTENSA | QEMU_ARCH_LM32 |

    QEMU_ARCH_MIPS)

STEXI

@item -semihosting

@findex -semihosting

Enable semihosting mode (ARM, M68K, Xtensa only).

Enable semihosting mode (ARM, M68K, Xtensa, MIPS only).

ETEXI

DEF("semihosting-config", HAS_ARG, QEMU_OPTION_semihosting_config,

    "-semihosting-config [enable=on|off][,target=native|gdb|auto][,arg=str[,...]]\n" \

    "                semihosting configuration\n",

QEMU_ARCH_ARM | QEMU_ARCH_M68K | QEMU_ARCH_XTENSA | QEMU_ARCH_LM32)

QEMU_ARCH_ARM | QEMU_ARCH_M68K | QEMU_ARCH_XTENSA | QEMU_ARCH_LM32 |

QEMU_ARCH_MIPS)

STEXI

@item -semihosting-config [enable=on|off][,target=native|gdb|auto][,arg=str[,...]]

@findex -semihosting-config

Enable and configure semihosting (ARM, M68K, Xtensa only).

Enable and configure semihosting (ARM, M68K, Xtensa, MIPS only).

@table @option

@item target=@code{native|gdb|auto}

Defines where the semihosting calls will be addressed, to QEMU (@code{native})

target-mips/Makefile.objs

+1 −1
Original line number Diff line number Diff line 
obj-y += translate.o dsp_helper.o op_helper.o lmi_helper.o helper.o cpu.o

obj-y += gdbstub.o msa_helper.o

obj-y += gdbstub.o msa_helper.o mips-semi.o

obj-$(CONFIG_SOFTMMU) += machine.o

obj-$(CONFIG_KVM) += kvm.o

target-mips/helper.h

+2 −0
Original line number Diff line number Diff line 
DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int)

DEF_HELPER_2(raise_exception, noreturn, env, i32)



DEF_HELPER_1(do_semihosting, void, env)



#ifdef TARGET_MIPS64

DEF_HELPER_4(sdl, void, env, tl, tl, int)

DEF_HELPER_4(sdr, void, env, tl, tl, int)