Commit cc523026 authored by Laurent Vivier's avatar Laurent Vivier
Browse files

target/m68k: fix m68k_cpu_dump_state() 



Display correctly the Trace bits for 680x0
(2 bits instead of 1 for Coldfire).

Signed-off-by: default avatarLaurent Vivier <laurent@vivier.eu>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-Id: <20180104012913.30763-18-laurent@vivier.eu>
parent 6e22b28e

target/m68k/cpu.h

+2 −1
Original line number Diff line number Diff line
@@ -219,7 +219,8 @@ typedef enum { 
#define SR_I  0x0700

#define SR_M  0x1000

#define SR_S  0x2000

#define SR_T  0x8000

#define SR_T_SHIFT 14

#define SR_T  0xc000



#define M68K_SSP    0

#define M68K_USP    1

target/m68k/translate.c

+6 −3
Original line number Diff line number Diff line
@@ -5936,9 +5936,12 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 
    }

    cpu_fprintf (f, "PC = %08x   ", env->pc);

    sr = env->sr | cpu_m68k_get_ccr(env);

    cpu_fprintf(f, "SR = %04x %c%c%c%c%c ", sr, (sr & CCF_X) ? 'X' : '-',

                (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',

                (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');

    cpu_fprintf(f, "SR = %04x T:%x I:%x %c%c %c%c%c%c%c\n",

                sr, (sr & SR_T) >> SR_T_SHIFT, (sr & SR_I) >> SR_I_SHIFT,

                (sr & SR_S) ? 'S' : 'U', (sr & SR_M) ? '%' : 'I',

                (sr & CCF_X) ? 'X' : '-', (sr & CCF_N) ? 'N' : '-',

                (sr & CCF_Z) ? 'Z' : '-', (sr & CCF_V) ? 'V' : '-',

                (sr & CCF_C) ? 'C' : '-');

    cpu_fprintf(f, "FPSR = %08x %c%c%c%c ", env->fpsr,

                (env->fpsr & FPSR_CC_A) ? 'A' : '-',

                (env->fpsr & FPSR_CC_I) ? 'I' : '-',