Unverified Commit cbf58276 authored by Michael Clark's avatar Michael Clark Committed by Palmer Dabbelt
Browse files

target/riscv: Implement riscv_cpu_unassigned_access 



This patch adds support for the riscv_cpu_unassigned_access call
and will raise a load or store access fault.

Signed-off-by: default avatarMichael Clark <mjc@sifive.com>
[Changes by AF:
 - Squash two patches and rewrite commit message
 - Set baddr to the access address
]
Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 49db9fa1

target/riscv/cpu.c

+1 −0
Original line number Diff line number Diff line
@@ -482,6 +482,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) 
    cc->gdb_stop_before_watchpoint = true;

    cc->disas_set_info = riscv_cpu_disas_set_info;

#ifndef CONFIG_USER_ONLY

    cc->do_unassigned_access = riscv_cpu_unassigned_access;

    cc->do_unaligned_access = riscv_cpu_do_unaligned_access;

    cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;

#endif

target/riscv/cpu.h

+2 −0
Original line number Diff line number Diff line
@@ -259,6 +259,8 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,

                        MMUAccessType access_type, int mmu_idx,

                        bool probe, uintptr_t retaddr);

void riscv_cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write,

                                 bool is_exec, int unused, unsigned size);

char *riscv_isa_string(RISCVCPU *cpu);

void riscv_cpu_list(void);

target/riscv/cpu_helper.c

+16 −0
Original line number Diff line number Diff line
@@ -375,6 +375,22 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 
    return phys_addr;

}



void riscv_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write,

                                 bool is_exec, int unused, unsigned size)

{

    RISCVCPU *cpu = RISCV_CPU(cs);

    CPURISCVState *env = &cpu->env;



    if (is_write) {

        cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;

    } else {

        cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;

    }



    env->badaddr = addr;

    riscv_raise_exception(&cpu->env, cs->exception_index, GETPC());

}



void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,

                                   MMUAccessType access_type, int mmu_idx,

                                   uintptr_t retaddr)