Commit cbdab58d authored Jun 27, 2016 by Alistair Francis Committed by Peter Maydell Jun 27, 2016

cadence_gem: Set the last bit when wrap is set



The Cadence GEM data sheet says:
"Wrap - marks last descriptor in transmit buffer descriptor list. This
can be set for any buffer within the frame."
which seems to imply that when the wrap bit is set so is the last bit.

Previously if the wrap bit is set, but the last is not then QEMU will
enter an infinite loop.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reported-by: Li Qiang <liqiang6-s@360.cn>
Reported-by: P J P <ppandit@redhat.com>
Message-id: eb23f15c67989ea6a53609dc66568399dadf52a7.1466539342.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

parent f265ae8c

hw/net/cadence_gem.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -274,6 +274,11 @@ static inline unsigned tx_desc_get_last(unsigned *desc)
		return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
		}

		static inline void tx_desc_set_last(unsigned *desc)
		{
		desc[1] \|= DESC_1_TX_LAST;
		}

		static inline unsigned tx_desc_get_length(unsigned *desc)
		{
		return desc[1] & DESC_1_LENGTH;
		@@ -939,6 +944,7 @@ static void gem_transmit(CadenceGEMState *s)

		/* read next descriptor */
		if (tx_desc_get_wrap(desc)) {
		tx_desc_set_last(desc);
		packet_desc_addr = s->regs[GEM_TXQBASE];
		} else {
		packet_desc_addr += 8;