Commit cb135f59 authored by Peter Xu's avatar Peter Xu Committed by Michael S. Tsirkin
Browse files

q35: ioapic: add support for emulated IOAPIC IR 

This patch translates all IOAPIC interrupts into MSI ones. One pseudo
ioapic address space is added to transfer the MSI message. By default,
it will be system memory address space. When IR is enabled, it will be
IOMMU address space.

Currently, only emulated IOAPIC is supported.

Idea suggested by Jan Kiszka and Rita Sinha in the following patch:

https://lists.gnu.org/archive/html/qemu-devel/2016-03/msg01933.html



Signed-off-by: default avatarPeter Xu <peterx@redhat.com>
Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
parent 09cd058a

hw/i386/intel_iommu.c

+5 −1
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include "hw/i386/pc.h"

#include "hw/boards.h"

#include "hw/i386/x86-iommu.h"

#include "hw/pci-host/q35.h"



/*#define DEBUG_INTEL_IOMMU*/

#ifdef DEBUG_INTEL_IOMMU
@@ -2367,7 +2368,8 @@ static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) 


static void vtd_realize(DeviceState *dev, Error **errp)

{

    PCIBus *bus = PC_MACHINE(qdev_get_machine())->bus;

    PCMachineState *pcms = PC_MACHINE(qdev_get_machine());

    PCIBus *bus = pcms->bus;

    IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);



    VTD_DPRINTF(GENERAL, "");
@@ -2383,6 +2385,8 @@ static void vtd_realize(DeviceState *dev, Error **errp) 
    vtd_init(s);

    sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);

    pci_setup_iommu(bus, vtd_host_dma_iommu, dev);

    /* Pseudo address space under root PCI bus. */

    pcms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC);

}



static void vtd_class_init(ObjectClass *klass, void *data)

hw/i386/pc.c

+3 −0
Original line number Diff line number Diff line
@@ -1475,6 +1475,9 @@ void pc_memory_init(PCMachineState *pcms, 
        rom_add_option(option_rom[i].name, option_rom[i].bootindex);

    }

    pcms->fw_cfg = fw_cfg;



    /* Init default IOAPIC address space */

    pcms->ioapic_as = &address_space_memory;

}



qemu_irq pc_allocate_cpu_irq(void)

hw/intc/ioapic.c

+24 −4
Original line number Diff line number Diff line
@@ -29,6 +29,8 @@ 
#include "hw/i386/ioapic_internal.h"

#include "include/hw/pci/msi.h"

#include "sysemu/kvm.h"

#include "target-i386/cpu.h"

#include "hw/i386/apic-msidef.h"



//#define DEBUG_IOAPIC
@@ -50,13 +52,15 @@ extern int ioapic_no; 


static void ioapic_service(IOAPICCommonState *s)

{

    AddressSpace *ioapic_as = PC_MACHINE(qdev_get_machine())->ioapic_as;

    uint32_t addr, data;

    uint8_t i;

    uint8_t trig_mode;

    uint8_t vector;

    uint8_t delivery_mode;

    uint32_t mask;

    uint64_t entry;

    uint8_t dest;

    uint16_t dest_idx;

    uint8_t dest_mode;



    for (i = 0; i < IOAPIC_NUM_PINS; i++) {
@@ -67,7 +71,14 @@ static void ioapic_service(IOAPICCommonState *s) 
            entry = s->ioredtbl[i];

            if (!(entry & IOAPIC_LVT_MASKED)) {

                trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);

                dest = entry >> IOAPIC_LVT_DEST_SHIFT;

                /*

                 * By default, this would be dest_id[8] +

                 * reserved[8]. When IR is enabled, this would be

                 * interrupt_index[15] + interrupt_format[1]. This

                 * field never means anything, but only used to

                 * generate corresponding MSI.

                 */

                dest_idx = entry >> IOAPIC_LVT_DEST_IDX_SHIFT;

                dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;

                delivery_mode =

                    (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
@@ -97,8 +108,17 @@ static void ioapic_service(IOAPICCommonState *s) 
#else

                (void)coalesce;

#endif

                apic_deliver_irq(dest, dest_mode, delivery_mode, vector,

                                 trig_mode);

                /* No matter whether IR is enabled, we translate

                 * the IOAPIC message into a MSI one, and its

                 * address space will decide whether we need a

                 * translation. */

                addr = APIC_DEFAULT_ADDRESS | \

                    (dest_idx << MSI_ADDR_DEST_IDX_SHIFT) |

                    (dest_mode << MSI_ADDR_DEST_MODE_SHIFT);

                data = (vector << MSI_DATA_VECTOR_SHIFT) |

                    (trig_mode << MSI_DATA_TRIGGER_SHIFT) |

                    (delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT);

                stl_le_phys(ioapic_as, addr, data);

            }

        }

    }

include/hw/i386/apic-msidef.h

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#define MSI_ADDR_REDIRECTION_SHIFT      3



#define MSI_ADDR_DEST_ID_SHIFT          12

#define MSI_ADDR_DEST_IDX_SHIFT         4

#define  MSI_ADDR_DEST_ID_MASK          0x00ffff0



#endif /* HW_APIC_MSIDEF_H */

include/hw/i386/ioapic_internal.h

+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#define IOAPIC_VERSION                  0x11



#define IOAPIC_LVT_DEST_SHIFT           56

#define IOAPIC_LVT_DEST_IDX_SHIFT       48

#define IOAPIC_LVT_MASKED_SHIFT         16

#define IOAPIC_LVT_TRIGGER_MODE_SHIFT   15

#define IOAPIC_LVT_REMOTE_IRR_SHIFT     14