Commit ca759f9e authored by Alex Bennée's avatar Alex Bennée
Browse files

tcg: enable MTTCG by default for ARM on x86 hosts 



This enables the multi-threaded system emulation by default for ARMv7
and ARMv8 guests using the x86_64 TCG backend. This is because on the
guest side:

  - The ARM translate.c/translate-64.c have been converted to
    - use MTTCG safe atomic primitives
    - emit the appropriate barrier ops
  - The ARM machine has been updated to
    - hold the BQL when modifying shared cross-vCPU state
    - defer powerctl changes to async safe work

All the host backends support the barrier and atomic primitives but
need to provide same-or-better support for normal load/store
operations.

Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
Acked-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Tested-by: default avatarPranith Kumar <bobby.prani@gmail.com>
Reviewed-by: default avatarPranith Kumar <bobby.prani@gmail.com>
parent 4881658a

configure

+6 −0
Original line number Diff line number Diff line
@@ -5879,6 +5879,7 @@ mkdir -p $target_dir 
echo "# Automatically generated by configure - do not modify" > $config_target_mak



bflt="no"

mttcg="no"

interp_prefix1=$(echo "$interp_prefix" | sed "s/%M/$target_name/g")

gdb_xml_files=""
@@ -5897,11 +5898,13 @@ case "$target_name" in 
  arm|armeb)

    TARGET_ARCH=arm

    bflt="yes"

    mttcg="yes"

    gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml"

  ;;

  aarch64)

    TARGET_BASE_ARCH=arm

    bflt="yes"

    mttcg="yes"

    gdb_xml_files="aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml"

  ;;

  cris)
@@ -6066,6 +6069,9 @@ if test "$target_bigendian" = "yes" ; then 
fi

if test "$target_softmmu" = "yes" ; then

  echo "CONFIG_SOFTMMU=y" >> $config_target_mak

  if test "$mttcg" = "yes" ; then

    echo "TARGET_SUPPORTS_MTTCG=y" >> $config_target_mak

  fi

fi

if test "$target_user_only" = "yes" ; then

  echo "CONFIG_USER_ONLY=y" >> $config_target_mak

target/arm/cpu.h

+3 −0
Original line number Diff line number Diff line
@@ -30,6 +30,9 @@ 
#  define TARGET_LONG_BITS 32

#endif



/* ARM processors have a weak memory model */

#define TCG_GUEST_DEFAULT_MO      (0)



#define CPUArchState struct CPUARMState



#include "qemu-common.h"

tcg/i386/tcg-target.h

+11 −0
Original line number Diff line number Diff line
@@ -165,4 +165,15 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) 
{

}



/* This defines the natural memory order supported by this

 * architecture before guarantees made by various barrier

 * instructions.

 *

 * The x86 has a pretty strong memory ordering which only really

 * allows for some stores to be re-ordered after loads.

 */

#include "tcg-mo.h"



#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)



#endif