Commit ca6c7803 authored by Petar Jovanovic's avatar Petar Jovanovic Committed by Leon Alrae
Browse files

target-mips: remove wrong checks for recip.fmt and rsqrt.fmt 



Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
they require any particular mode for its FPU. This patch removes the checks
that may break a program that uses these instructions.

Signed-off-by: default avatarPetar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
Signed-off-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
parent 71f303cd

target-mips/translate.c

+2 −4
Original line number Diff line number Diff line
@@ -9290,7 +9290,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, 
        opn = "movn.s";

        break;

    case OPC_RECIP_S:

        check_cop1x(ctx);

        {

            TCGv_i32 fp0 = tcg_temp_new_i32();








@@ -9302,7 +9301,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,







        opn = "recip.s";









        break;









    case OPC_RSQRT_S:









        check_cop1x(ctx);









        {









            TCGv_i32 fp0 = tcg_temp_new_i32();
















@@ -9835,7 +9833,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,







        opn = "movn.d";









        break;









    case OPC_RECIP_D:









        check_cp1_64bitmode(ctx);









        check_cp1_registers(ctx, fs | fd);









        {









            TCGv_i64 fp0 = tcg_temp_new_i64();
















@@ -9847,7 +9845,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,







        opn = "recip.d";









        break;









    case OPC_RSQRT_D:









        check_cp1_64bitmode(ctx);









        check_cp1_registers(ctx, fs | fd);









        {









            TCGv_i64 fp0 = tcg_temp_new_i64();