Commit ca4e4b82 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/rth/tags/pull-tile-20151007' into staging



Collected patches

# gpg: Signature made Wed 07 Oct 2015 10:30:17 BST using RSA key ID 4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"

* remotes/rth/tags/pull-tile-20151007:
  target-tilegx: Support iret instruction and related special registers
  target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN and TILEGX_EXCP_OPCODE_UNIMPLEMENTED correctly
  target-tilegx: Implement v2mults instruction
  target-tilegx: Implement v?int_* instructions.
  target-tilegx: Implement v2sh* instructions
  target-tilegx: Handle nofault prefetch instructions
  target-tilegx: Fix a typo for mnemonic about "ld_add"
  target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGV
  target-tilegx: Decode ill pseudo-instructions
  linux-user/tilegx: Implement tilegx signal features
  linux-user/syscall_defs.h: Sync the latest si_code from Linux kernel
  target-tilegx: Let x1 pipe process bpt instruction only
  target-tilegx: Implement complex multiply instructions
  target-tilegx: Implement table index instructions
  target-tilegx: Implement crc instructions
  target-tilegx: Implement v1multu instruction
  target-tilegx: Implement v*add and v*sub instructions
  target-tilegx: Implement v*shl, v*shru, and v*shrs instructions
  target-tilegx: Tidy simd_helper.c

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents fb6345f4 fec7daab
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+29 −10
Original line number Diff line number Diff line
@@ -3414,28 +3414,47 @@ void cpu_loop(CPUS390XState *env)

#ifdef TARGET_TILEGX

static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
static void gen_sigill_reg(CPUTLGState *env)
{
    target_siginfo_t info;

    info.si_signo = TARGET_SIGSEGV;
    info.si_signo = TARGET_SIGILL;
    info.si_errno = 0;
    info.si_code = TARGET_SEGV_MAPERR;
    info._sifields._sigfault._addr = addr;
    info.si_code = TARGET_ILL_PRVREG;
    info._sifields._sigfault._addr = env->pc;
    queue_signal(env, info.si_signo, &info);
}

static void gen_sigill_reg(CPUTLGState *env)
static void do_signal(CPUTLGState *env, int signo, int sigcode)
{
    target_siginfo_t info;

    info.si_signo = TARGET_SIGILL;
    info.si_signo = signo;
    info.si_errno = 0;
    info.si_code = TARGET_ILL_PRVREG;
    info._sifields._sigfault._addr = env->pc;

    if (signo == TARGET_SIGSEGV) {
        /* The passed in sigcode is a dummy; check for a page mapping
           and pass either MAPERR or ACCERR.  */
        target_ulong addr = env->excaddr;
        info._sifields._sigfault._addr = addr;
        if (page_check_range(addr, 1, PAGE_VALID) < 0) {
            sigcode = TARGET_SEGV_MAPERR;
        } else {
            sigcode = TARGET_SEGV_ACCERR;
        }
    }
    info.si_code = sigcode;

    queue_signal(env, info.si_signo, &info);
}

static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
{
    env->excaddr = addr;
    do_signal(env, TARGET_SIGSEGV, 0);
}

static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
{
    if (unlikely(reg >= TILEGX_R_COUNT)) {
@@ -3622,13 +3641,13 @@ void cpu_loop(CPUTLGState *env)
        case TILEGX_EXCP_OPCODE_FETCHOR4:
            do_fetch(env, trapnr, false);
            break;
        case TILEGX_EXCP_SIGNAL:
            do_signal(env, env->signo, env->sigcode);
            break;
        case TILEGX_EXCP_REG_IDN_ACCESS:
        case TILEGX_EXCP_REG_UDN_ACCESS:
            gen_sigill_reg(env);
            break;
        case TILEGX_EXCP_SEGV:
            gen_sigsegv_maperr(env, env->excaddr);
            break;
        default:
            fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
            g_assert_not_reached();
+158 −1
Original line number Diff line number Diff line
@@ -5537,6 +5537,163 @@ long do_rt_sigreturn(CPUAlphaState *env)
    force_sig(TARGET_SIGSEGV);
}

#elif defined(TARGET_TILEGX)

struct target_sigcontext {
    union {
        /* General-purpose registers.  */
        abi_ulong gregs[56];
        struct {
            abi_ulong __gregs[53];
            abi_ulong tp;        /* Aliases gregs[TREG_TP].  */
            abi_ulong sp;        /* Aliases gregs[TREG_SP].  */
            abi_ulong lr;        /* Aliases gregs[TREG_LR].  */
        };
    };
    abi_ulong pc;        /* Program counter.  */
    abi_ulong ics;       /* In Interrupt Critical Section?  */
    abi_ulong faultnum;  /* Fault number.  */
    abi_ulong pad[5];
};

struct target_ucontext {
    abi_ulong tuc_flags;
    abi_ulong tuc_link;
    target_stack_t tuc_stack;
    struct target_sigcontext tuc_mcontext;
    target_sigset_t tuc_sigmask;   /* mask last for extensibility */
};

struct target_rt_sigframe {
    unsigned char save_area[16]; /* caller save area */
    struct target_siginfo info;
    struct target_ucontext uc;
};

static void setup_sigcontext(struct target_sigcontext *sc,
                             CPUArchState *env, int signo)
{
    int i;

    for (i = 0; i < TILEGX_R_COUNT; ++i) {
        __put_user(env->regs[i], &sc->gregs[i]);
    }

    __put_user(env->pc, &sc->pc);
    __put_user(0, &sc->ics);
    __put_user(signo, &sc->faultnum);
}

static void restore_sigcontext(CPUTLGState *env, struct target_sigcontext *sc)
{
    int i;

    for (i = 0; i < TILEGX_R_COUNT; ++i) {
        __get_user(env->regs[i], &sc->gregs[i]);
    }

    __get_user(env->pc, &sc->pc);
}

static abi_ulong get_sigframe(struct target_sigaction *ka, CPUArchState *env,
                              size_t frame_size)
{
    unsigned long sp = env->regs[TILEGX_R_SP];

    if (on_sig_stack(sp) && !likely(on_sig_stack(sp - frame_size))) {
        return -1UL;
    }

    if ((ka->sa_flags & SA_ONSTACK) && !sas_ss_flags(sp)) {
        sp = target_sigaltstack_used.ss_sp + target_sigaltstack_used.ss_size;
    }

    sp -= frame_size;
    sp &= -16UL;
    return sp;
}

static void setup_rt_frame(int sig, struct target_sigaction *ka,
                           target_siginfo_t *info,
                           target_sigset_t *set, CPUArchState *env)
{
    abi_ulong frame_addr;
    struct target_rt_sigframe *frame;
    unsigned long restorer;

    frame_addr = get_sigframe(ka, env, sizeof(*frame));
    if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) {
        goto give_sigsegv;
    }

    /* Always write at least the signal number for the stack backtracer. */
    if (ka->sa_flags & TARGET_SA_SIGINFO) {
        /* At sigreturn time, restore the callee-save registers too. */
        tswap_siginfo(&frame->info, info);
        /* regs->flags |= PT_FLAGS_RESTORE_REGS; FIXME: we can skip it? */
    } else {
        __put_user(info->si_signo, &frame->info.si_signo);
    }

    /* Create the ucontext.  */
    __put_user(0, &frame->uc.tuc_flags);
    __put_user(0, &frame->uc.tuc_link);
    __put_user(target_sigaltstack_used.ss_sp, &frame->uc.tuc_stack.ss_sp);
    __put_user(sas_ss_flags(env->regs[TILEGX_R_SP]),
               &frame->uc.tuc_stack.ss_flags);
    __put_user(target_sigaltstack_used.ss_size, &frame->uc.tuc_stack.ss_size);
    setup_sigcontext(&frame->uc.tuc_mcontext, env, info->si_signo);

    restorer = (unsigned long) do_rt_sigreturn;
    if (ka->sa_flags & TARGET_SA_RESTORER) {
            restorer = (unsigned long) ka->sa_restorer;
    }
    env->pc = (unsigned long) ka->_sa_handler;
    env->regs[TILEGX_R_SP] = (unsigned long) frame;
    env->regs[TILEGX_R_LR] = restorer;
    env->regs[0] = (unsigned long) sig;
    env->regs[1] = (unsigned long) &frame->info;
    env->regs[2] = (unsigned long) &frame->uc;
    /* regs->flags |= PT_FLAGS_CALLER_SAVES; FIXME: we can skip it? */

    unlock_user_struct(frame, frame_addr, 1);
    return;

give_sigsegv:
    if (sig == TARGET_SIGSEGV) {
        ka->_sa_handler = TARGET_SIG_DFL;
    }
    force_sig(TARGET_SIGSEGV /* , current */);
}

long do_rt_sigreturn(CPUTLGState *env)
{
    abi_ulong frame_addr = env->regs[TILEGX_R_SP];
    struct target_rt_sigframe *frame;
    sigset_t set;

    if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) {
        goto badframe;
    }
    target_to_host_sigset(&set, &frame->uc.tuc_sigmask);
    do_sigprocmask(SIG_SETMASK, &set, NULL);

    restore_sigcontext(env, &frame->uc.tuc_mcontext);
    if (do_sigaltstack(frame_addr + offsetof(struct target_rt_sigframe,
                                             uc.tuc_stack),
                       0, env->regs[TILEGX_R_SP]) == -EFAULT) {
        goto badframe;
    }

    unlock_user_struct(frame, frame_addr, 0);
    return env->regs[TILEGX_R_RE];


 badframe:
    unlock_user_struct(frame, frame_addr, 0);
    force_sig(TARGET_SIGSEGV);
}

#else

static void setup_frame(int sig, struct target_sigaction *ka,
@@ -5657,7 +5814,7 @@ void process_pending_signals(CPUArchState *cpu_env)
#endif
        /* prepare the stack frame of the virtual CPU */
#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) \
    || defined(TARGET_OPENRISC)
    || defined(TARGET_OPENRISC) || defined(TARGET_TILEGX)
        /* These targets do not have traditional signals.  */
        setup_rt_frame(sig, sa, &q->info, &target_old_set, cpu_env);
#else
+11 −0
Original line number Diff line number Diff line
@@ -748,6 +748,10 @@ typedef struct target_siginfo {
#define TARGET_ILL_PRVREG	(6)	/* privileged register */
#define TARGET_ILL_COPROC	(7)	/* coprocessor error */
#define TARGET_ILL_BADSTK	(8)	/* internal stack error */
#ifdef TARGET_TILEGX
#define TARGET_ILL_DBLFLT       (9)     /* double fault */
#define TARGET_ILL_HARDWALL     (10)    /* user networks hardwall violation */
#endif

/*
 * SIGFPE si_codes
@@ -767,6 +771,7 @@ typedef struct target_siginfo {
 */
#define TARGET_SEGV_MAPERR     (1)  /* address not mapped to object */
#define TARGET_SEGV_ACCERR     (2)  /* invalid permissions for mapped object */
#define TARGET_SEGV_BNDERR     (3)  /* failed address bound checks */

/*
 * SIGBUS si_codes
@@ -774,12 +779,18 @@ typedef struct target_siginfo {
#define TARGET_BUS_ADRALN       (1)	/* invalid address alignment */
#define TARGET_BUS_ADRERR       (2)	/* non-existent physical address */
#define TARGET_BUS_OBJERR       (3)	/* object specific hardware error */
/* hardware memory error consumed on a machine check: action required */
#define TARGET_BUS_MCEERR_AR    (4)
/* hardware memory error detected in process but not consumed: action optional*/
#define TARGET_BUS_MCEERR_AO    (5)

/*
 * SIGTRAP si_codes
 */
#define TARGET_TRAP_BRKPT	(1)	/* process breakpoint */
#define TARGET_TRAP_TRACE	(2)	/* process trace trap */
#define TARGET_TRAP_BRANCH      (3)     /* process taken branch trap */
#define TARGET_TRAP_HWBKPT      (4)     /* hardware breakpoint/watchpoint */

#endif /* defined(TARGET_I386) || defined(TARGET_ARM) */

+3 −0
Original line number Diff line number Diff line
@@ -37,4 +37,7 @@ struct target_pt_regs {
#define TARGET_MLOCKALL_MCL_CURRENT 1
#define TARGET_MLOCKALL_MCL_FUTURE  2

/* For faultnum */
#define TARGET_INT_SWINT_1            14

#endif
+6 −1
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@
#include "qemu-common.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "linux-user/syscall_defs.h"

static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
                                  fprintf_function cpu_fprintf, int flags)
@@ -121,8 +122,12 @@ static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
{
    TileGXCPU *cpu = TILEGX_CPU(cs);

    cs->exception_index = TILEGX_EXCP_SEGV;
    /* The sigcode field will be filled in by do_signal in main.c.  */
    cs->exception_index = TILEGX_EXCP_SIGNAL;
    cpu->env.excaddr = address;
    cpu->env.signo = TARGET_SIGSEGV;
    cpu->env.sigcode = 0;

    return 1;
}

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