Commit c9ebc75d authored by BALATON Zoltan's avatar BALATON Zoltan Committed by John Snow
Browse files

cmd646: Move PCI IDE specific functions to ide/pci.c 



The io mem ops callbacks are not specific to CMD646 but really follow
the PCI IDE spec so move these from cmd646.c to pci.c to allow other
PCI IDE implementations to use them.

Signed-off-by: default avatarBALATON Zoltan <balaton@eik.bme.hu>
Tested-by: default avatarMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: default avatarJohn Snow <jsnow@redhat.com>
Message-id: a2b1b2b74afdc78330b8b75605687f683a249635.1547166960.git.balaton@eik.bme.hu
Signed-off-by: default avatarJohn Snow <jsnow@redhat.com>
parent e210ec87

hw/ide/cmd646.c

+2 −69
Original line number Diff line number Diff line
@@ -50,81 +50,14 @@ 


static void cmd646_update_irq(PCIDevice *pd);



static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,

                                unsigned size)

{

    IDEBus *bus = opaque;



    if (addr != 2 || size != 1) {

        return ((uint64_t)1 << (size * 8)) - 1;

    }

    return ide_status_read(bus, addr + 2);

}



static void cmd646_cmd_write(void *opaque, hwaddr addr,

                             uint64_t data, unsigned size)

{

    IDEBus *bus = opaque;



    if (addr != 2 || size != 1) {

        return;

    }

    ide_cmd_write(bus, addr + 2, data);

}



static const MemoryRegionOps cmd646_cmd_ops = {

    .read = cmd646_cmd_read,

    .write = cmd646_cmd_write,

    .endianness = DEVICE_LITTLE_ENDIAN,

};



static uint64_t cmd646_data_read(void *opaque, hwaddr addr,

                                 unsigned size)

{

    IDEBus *bus = opaque;



    if (size == 1) {

        return ide_ioport_read(bus, addr);

    } else if (addr == 0) {

        if (size == 2) {

            return ide_data_readw(bus, addr);

        } else {

            return ide_data_readl(bus, addr);

        }

    }

    return ((uint64_t)1 << (size * 8)) - 1;

}



static void cmd646_data_write(void *opaque, hwaddr addr,

                             uint64_t data, unsigned size)

{

    IDEBus *bus = opaque;



    if (size == 1) {

        ide_ioport_write(bus, addr, data);

    } else if (addr == 0) {

        if (size == 2) {

            ide_data_writew(bus, addr, data);

        } else {

            ide_data_writel(bus, addr, data);

        }

    }

}



static const MemoryRegionOps cmd646_data_ops = {

    .read = cmd646_data_read,

    .write = cmd646_data_write,

    .endianness = DEVICE_LITTLE_ENDIAN,

};



static void setup_cmd646_bar(PCIIDEState *d, int bus_num)

{

    IDEBus *bus = &d->bus[bus_num];

    CMD646BAR *bar = &d->cmd646_bar[bus_num];



    memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bus,

    memory_region_init_io(&bar->cmd, OBJECT(d), &pci_ide_cmd_le_ops, bus,

                          "cmd646-cmd", 4);

    memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bus,

    memory_region_init_io(&bar->data, OBJECT(d), &pci_ide_data_le_ops, bus,

                          "cmd646-data", 8);

}

hw/ide/pci.c

+65 −0
Original line number Diff line number Diff line
@@ -36,6 +36,71 @@ 
        (IDE_RETRY_DMA | IDE_RETRY_PIO | \

        IDE_RETRY_READ | IDE_RETRY_FLUSH)



static uint64_t pci_ide_cmd_read(void *opaque, hwaddr addr, unsigned size)

{

    IDEBus *bus = opaque;



    if (addr != 2 || size != 1) {

        return ((uint64_t)1 << (size * 8)) - 1;

    }

    return ide_status_read(bus, addr + 2);

}



static void pci_ide_cmd_write(void *opaque, hwaddr addr,

                              uint64_t data, unsigned size)

{

    IDEBus *bus = opaque;



    if (addr != 2 || size != 1) {

        return;

    }

    ide_cmd_write(bus, addr + 2, data);

}



const MemoryRegionOps pci_ide_cmd_le_ops = {

    .read = pci_ide_cmd_read,

    .write = pci_ide_cmd_write,

    .endianness = DEVICE_LITTLE_ENDIAN,

};



static uint64_t pci_ide_data_read(void *opaque, hwaddr addr, unsigned size)

{

    IDEBus *bus = opaque;



    if (size == 1) {

        return ide_ioport_read(bus, addr);

    } else if (addr == 0) {

        if (size == 2) {

            return ide_data_readw(bus, addr);

        } else {

            return ide_data_readl(bus, addr);

        }

    }

    return ((uint64_t)1 << (size * 8)) - 1;

}



static void pci_ide_data_write(void *opaque, hwaddr addr,

                               uint64_t data, unsigned size)

{

    IDEBus *bus = opaque;



    if (size == 1) {

        ide_ioport_write(bus, addr, data);

    } else if (addr == 0) {

        if (size == 2) {

            ide_data_writew(bus, addr, data);

        } else {

            ide_data_writel(bus, addr, data);

        }

    }

}



const MemoryRegionOps pci_ide_data_le_ops = {

    .read = pci_ide_data_read,

    .write = pci_ide_data_write,

    .endianness = DEVICE_LITTLE_ENDIAN,

};



static void bmdma_start_dma(IDEDMA *dma, IDEState *s,

                            BlockCompletionFunc *dma_cb)

{

include/hw/ide/pci.h

+2 −0
Original line number Diff line number Diff line
@@ -71,4 +71,6 @@ extern MemoryRegionOps bmdma_addr_ioport_ops; 
void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table);



extern const VMStateDescription vmstate_ide_pci;

extern const MemoryRegionOps pci_ide_cmd_le_ops;

extern const MemoryRegionOps pci_ide_data_le_ops;

#endif