Unverified Commit c9a73910 authored by Alistair Francis's avatar Alistair Francis Committed by Palmer Dabbelt
Browse files

target/riscv: Remove user version information 



Remove the user version information. This was never used and never
publically exposed in a release of QEMU, so let's just remove it. In
future to manage versions we can extend the extension properties to
specify version.

Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent bdddd446

target/riscv/cpu.c

+9 −23
Original line number Diff line number Diff line
@@ -89,9 +89,8 @@ static void set_misa(CPURISCVState *env, target_ulong misa) 
    env->misa_mask = env->misa = misa;

}



static void set_versions(CPURISCVState *env, int user_ver, int priv_ver)

static void set_priv_version(CPURISCVState *env, int priv_ver)

{

    env->user_ver = user_ver;

    env->priv_ver = priv_ver;

}
@@ -111,7 +110,7 @@ static void riscv_any_cpu_init(Object *obj) 
{

    CPURISCVState *env = &RISCV_CPU(obj)->env;

    set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);

    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_11_0);

    set_priv_version(env, PRIV_VERSION_1_11_0);

    set_resetvec(env, DEFAULT_RSTVEC);

}
@@ -128,7 +127,7 @@ static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) 
{

    CPURISCVState *env = &RISCV_CPU(obj)->env;

    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);

    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1);

    set_priv_version(env, PRIV_VERSION_1_09_1);

    set_resetvec(env, DEFAULT_RSTVEC);

    set_feature(env, RISCV_FEATURE_MMU);

    set_feature(env, RISCV_FEATURE_PMP);
@@ -138,7 +137,7 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) 
{

    CPURISCVState *env = &RISCV_CPU(obj)->env;

    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);

    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);

    set_priv_version(env, PRIV_VERSION_1_10_0);

    set_resetvec(env, DEFAULT_RSTVEC);

    set_feature(env, RISCV_FEATURE_MMU);

    set_feature(env, RISCV_FEATURE_PMP);
@@ -148,7 +147,7 @@ static void rv32imacu_nommu_cpu_init(Object *obj) 
{

    CPURISCVState *env = &RISCV_CPU(obj)->env;

    set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);

    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);

    set_priv_version(env, PRIV_VERSION_1_10_0);

    set_resetvec(env, DEFAULT_RSTVEC);

    set_feature(env, RISCV_FEATURE_PMP);

}
@@ -166,7 +165,7 @@ static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) 
{

    CPURISCVState *env = &RISCV_CPU(obj)->env;

    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);

    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1);

    set_priv_version(env, PRIV_VERSION_1_09_1);

    set_resetvec(env, DEFAULT_RSTVEC);

    set_feature(env, RISCV_FEATURE_MMU);

    set_feature(env, RISCV_FEATURE_PMP);
@@ -176,7 +175,7 @@ static void rv64gcsu_priv1_10_0_cpu_init(Object *obj) 
{

    CPURISCVState *env = &RISCV_CPU(obj)->env;

    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);

    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);

    set_priv_version(env, PRIV_VERSION_1_10_0);

    set_resetvec(env, DEFAULT_RSTVEC);

    set_feature(env, RISCV_FEATURE_MMU);

    set_feature(env, RISCV_FEATURE_PMP);
@@ -186,7 +185,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj) 
{

    CPURISCVState *env = &RISCV_CPU(obj)->env;

    set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);

    set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);

    set_priv_version(env, PRIV_VERSION_1_10_0);

    set_resetvec(env, DEFAULT_RSTVEC);

    set_feature(env, RISCV_FEATURE_PMP);

}
@@ -317,7 +316,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) 
    CPURISCVState *env = &cpu->env;

    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);

    int priv_version = PRIV_VERSION_1_11_0;

    int user_version = USER_VERSION_2_02_0;

    target_ulong target_misa = 0;

    Error *local_err = NULL;
@@ -342,18 +340,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) 
        }

    }



    if (cpu->cfg.user_spec) {

        if (!g_strcmp0(cpu->cfg.user_spec, "v2.02.0")) {

            user_version = USER_VERSION_2_02_0;

        } else {

            error_setg(errp,

                       "Unsupported user spec version '%s'",

                       cpu->cfg.user_spec);

            return;

        }

    }



    set_versions(env, user_version, priv_version);

    set_priv_version(env, priv_version);

    set_resetvec(env, DEFAULT_RSTVEC);



    if (cpu->cfg.mmu) {
@@ -454,7 +441,6 @@ static Property riscv_cpu_properties[] = { 
    DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),

    DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),

    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),

    DEFINE_PROP_STRING("user_spec", RISCVCPU, cfg.user_spec),

    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),

    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),

    DEFINE_PROP_END_OF_LIST(),

target/riscv/cpu.h

+0 −2
Original line number Diff line number Diff line
@@ -78,7 +78,6 @@ enum { 
    RISCV_FEATURE_MISA

};



#define USER_VERSION_2_02_0 0x00020200

#define PRIV_VERSION_1_09_1 0x00010901

#define PRIV_VERSION_1_10_0 0x00011000

#define PRIV_VERSION_1_11_0 0x00011100
@@ -105,7 +104,6 @@ struct CPURISCVState { 


    target_ulong badaddr;



    target_ulong user_ver;

    target_ulong priv_ver;

    target_ulong misa;

    target_ulong misa_mask;